synchronous and asynchronous

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s_vlsi

Joined: 16 May 2006
Posts: 21

26 May 2006 13:56 synchronous and asynchronous

can anyone tell me the difference between synchronous and aynsynchronous reset with the verilog code ?
which reset should we go for? Question

Thanks & Regards

sree205

Joined: 13 Mar 2006
Posts: 421
Helped: 30

27 May 2006 8:40 synchronous and asynchronous

why don't u read the paper on resets by clifford cummings? this link has a paper on resets, this will help your understanding.

http://www.sunburst-design.com/papers/

louisnells

Joined: 08 May 2006
Posts: 212
Helped: 13

27 May 2006 13:27 Re: synchronous and asynchronous

In synchronous one reset is happening only when clock is active (either on +ve going or -ve going pulse). ie: you have put the reset signal until the clock edge samples it.
But in asynchronous reset reset happens instantaneously.

zainmirza

Joined: 24 Dec 2005
Posts: 134
Helped: 32
Location: Islamabad

27 May 2006 19:11 synchronous and asynchronous

plz also write abt the transmission i.e Synchronous and Asynchronous Transmission.

louisnells

Joined: 08 May 2006
Posts: 212
Helped: 13

27 May 2006 19:30 Re: synchronous and asynchronous

If the transmission is synchrounous there will be some reference signal (clock) which makes the peers involved in the communication step in unison. The ICSP connection from the PIC programmer to the µC is synchronous, because there is a reference clock in ICSP.
In asynchronous transmission there won't be any such refernce signal. For example RS232 no clock signal at-all.

zainmirza wrote:

plz also write abt the transmission i.e Synchronous and Asynchronous Transmission.

dsocer

Joined: 04 Apr 2006
Posts: 11

29 May 2006 4:45 Re: synchronous and asynchronous

synchronous: always@(posedge clk )
begin
if(rst==0) ......
else ..............
end

asynchronous:always@(posedge clk or negedge rst)

I think synchronous is better in most applications.

sree205

Joined: 13 Mar 2006
Posts: 421
Helped: 30

30 May 2006 12:36 synchronous and asynchronous

Incase of obtaining an asynchronous input, the way to make it synchronize without any metastability is to double flop the asynchronous input and to use the output of the second flop in the design.

The same method also applies to a signal traversing from one clock domain to another.

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shankarmit

Joined: 22 Jun 2005
Posts: 188
Helped: 8
Location: India

30 May 2006 14:13 Re: synchronous and asynchronous

Asynchornous reset is irrespective of clock and reset will act..

use if reset=1 then..

elsif(alway(at)clock)..

In synchronous reset.. only if clock is active(postive or negative).. and reset will act

if(alwy(at)clocl)
if(reset)..

sorry I am not good in verilog.. u write in this manner..

Regards
Shankar

eelinker

Joined: 12 Feb 2006
Posts: 572
Helped: 12
Location: PERSIA

21 Jul 2006 6:31 synchronous and asynchronous

In the name of ---
diffrences are:
1)asynchronus has no clock and based on gates delay rather than flip-flop .
2)asynchronus is not supported by CAD tools, so it is not wise to design asynchronous.
3)for more information on asynchronous designing refer to ASCnotes.pdf in the web.
regards

vcnvcc

Joined: 21 Jul 2006
Posts: 88
Helped: 1

21 Jul 2006 9:21 Re: synchronous and asynchronous

few points abt reset synch. and Async

1. Asynch reset is fast compare to sync, takes less hardware, takes less power ,But
chances are there for timing violation for Async reset.

bansalr

Joined: 22 Dec 2005
Posts: 158
Helped: 13

21 Jul 2006 10:19 Re: synchronous and asynchronous

Plz go to the link below to have more discussion on async vs sync

http://www.deepchip.com/items/0396-01.html

kaustubhkhole

Joined: 21 Jan 2006
Posts: 102

23 Jul 2006 18:34 synchronous and asynchronous

Clock and without clock !!!
this is the simplest def.....

haytham

Joined: 06 Jun 2004
Posts: 225
Helped: 14
Location: Egypt

23 Jul 2006 21:53 Re: synchronous and asynchronous

Hi
Synchronous reset means to sample the reset with the clock edge (either pos or neg)
While Asynchronous reset means to reset when ever the reset condition is active.
An important issue on asynchrounous reset is that it should e removed synchrnously from the module reset input and this is considered as an issue on system integration.

the following Verilog is correct

Quote:

synchronous: always@(posedge clk )
begin
if(rst==0) ......
else ..............
end

asynchronous:always@(posedge clk or negedge rst)

For digital IC design, we always use the asynchrnous reset

For synchronous transmission means that clock signal is transferred with the data while asynchronous one means no clock info at all.

In asynchrnous transmission, clock is re-extracted fom data using CDR circuit (clock-data recovery) and then data is synchronized with clock of receiver domain using 2 FF's at least

Thanks