au_sun
Joined: 05 Aug 2004
Posts: 148
Helped: 10
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 08 May 2006 7:55 Re: what is the influence of dummy metal for metal density |
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The Below information was taken from a paper abstract,
"In very deep-submicron VLSI, certain manufacturing steps – notably
optical exposure, resist development and etch, chemical vapor deposition
and chemical-mechanical polishing (CMP)– have varying effects
on device and interconnect features depending on local characteristics
of the layout. To make these effects uniform and predictable, the layout
itself must be made uniform with respect to certain density parameters.
Traditionally, only foundries have performed the post-processing
needed to achieve this uniformity, via insertion (“filling”) or partial
deletion (“slotting”) of features in the layout. Today, however, physical
design and verification tools cannot remain oblivious to such foundry
post-processing. Without an accurate estimate of the filling and slotting,
RC extraction, delay calculation, and timing and noise analysis
flows will all suffer from wild inaccuracies. Therefore, future placeand-
route tools must efficiently perform filling and slotting prior to
performance analysis within the layout optimization loop."
For ur Kind information,
I would like to mention that the Dummy metal and poly is added at the final stage of P&R after the STA, As the Technology scaling reaches to the 90nm, 65nm etc, the Parasitics due to these Dummy Metals started to play a spoil game on the Timing of the Design, So EDA people are working on How to place Dummy metal in the Chip without affectiing the Timing of the Design.
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wkong_zhu
Joined: 13 Nov 2004
Posts: 171
Helped: 2
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08 May 2006 14:50 what is the influence of dummy metal for metal density |
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| au_sun thanks for your good information. By now, I use 0.18um tech. , and EDA tools can't take this issue into account. Because tech is 0.18um, maybe the effects are not so salient.
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