I want design a SAR ADC can somebody give some advice ~~~

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chungming

Joined: 23 Mar 2006
Posts: 100
Helped: 7

26 Apr 2006 10:20 sar adc

I am not familiar with SAR ADC
Can somone to give me some advice
My spec is DC to 1K Hz bandwidth about 12bits and low power.
can someone give me some advice
thanks ~~~!!

Vamsi Mocherla

Joined: 06 Sep 2004
Posts: 482
Helped: 62

26 Apr 2006 11:42 I want design a SAR ADC can somebody give some advice ~~~

Try the maxim website for SAR ADCs. They have very good information there. The following is the hyperlink

http://www.maxim-ic.com/appnotes.cfm/appnote_number/1080

jerryzhao

Joined: 08 Oct 2005
Posts: 159
Helped: 19

28 Apr 2006 15:13 Re: I want design a SAR ADC can somebody give some advice ~

Architecture use the capacitor array(charge redistribution). Take care of comparator's resoltion and the match of capacitor arry) . the 12bit's resolution is not easy.

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jerryzhao

Joined: 08 Oct 2005
Posts: 159
Helped: 19

02 May 2006 11:18 I want design a SAR ADC can somebody give some advice ~~~

The comparator use two or three stage with capacitor couple then connect latch. the first's gain not high use the doide connecting loading to reduce the nolinear error.
Second: consider the capacitor nolinear if u use capacitor array(charge redistribution).

SkyHigh

Joined: 13 Jan 2005
Posts: 376
Helped: 51

02 May 2006 11:33 Re: I want design a SAR ADC can somebody give some advice ~

I agree with jerryzhao.

Books tell everyone how good is capacitor array for charge redistribution.

I would say let's wait untill you try matching the metal layer L x W in Cadence Virtuoso and compare after you added the CMOS process error (usually 10%) in MIM capacitor, and measured the leakage power due to parasitic, you will start to panick.

For SAR more than 8-bit, try not to use capacitor array.
Use the resistor-ladder with low resistor ratio.
See Ken Martin's book that talks about re-arrange resistors to reduce resistor ratio.
In this way, you can avoid using high resistor values, still reaonably good matching that offers lower leakage current.

If you want, I remember Professor Boser and his students from UC-Berkeley published a paper on Smart Dust SAR in Journal Solid-State Circuits 2005 May. It is a good paper to refer.