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verilog hdl--- instantiation
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param



Joined: 09 Sep 2005
Posts: 46
Helped: 4
Post12 Apr 2006 6:45   

verilog hdl, instantiation
hi,
how to instantiate a module in another module with output port of the the instantiated module to map the input port of instantiating module...
let me give an example...
there are two modules xxx and yyy;

module xxx (in1,in2, out);
input in1,in2;
output out;
endmodule

module yyy(a,b,c);
input a,b;
output c;
endmodule

now i want output 'out' of xxx module to be connected to input 'a' of module yyy;
i.e., a<=out;
i tried like...
module yyy(a,b,c);
input a,b;
output c;
xxx ttt(.out(a));
endmodule

it dint work...

plese help regarding this doubt, in anticipation of ur help,
thanx in advance
take care
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it_boy



Joined: 18 Jul 2002
Posts: 181
Helped: 4
Post12 Apr 2006 7:31   

verilog instantiation -vhdl
Try this..

module zzz;
wire in1, in2, out, b, c;
xxx xxx_inst (in1,in2, out);
yyy yyy_inst (out,b,c);

endmodule
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