Concatenate String in Verilog?

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davyzhu

Joined: 23 May 2004
Posts: 521
Helped: 3
Location: oriental

01 Apr 2006 2:40 verilog concatenation

Hi all,
I want to open a lot of files and read data to reg.

something like
//-----code--------
$readmemh(".\pattern\0.dat",inmem0);
$readmemh(".\pattern\1.dat",inmem1);
...
$readmemh(".\pattern\49.dat",inmem49);
//-----code end----

I want to use something like strcat() in C to concatenate the string.
So, I can use a loop to replace large block of code above.
Is there any method to do this work in Verilog?

Any suggestions will be appreciated!
Best regards,
Davy

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funzero

Joined: 19 Nov 2004
Posts: 204
Helped: 8

01 Apr 2006 6:17 verilog string concatenation

you can try this:
case(i):
0: begin $readmemh("./pattern/mem_0.dat, mem0_reg);end
1:begin $readmemh("./pattern/mem_1.dat,mem1_reg);end
default: begin $display(" Nothing to Open " ); end
endcase

jarodz

Joined: 12 Mar 2005
Posts: 100
Helped: 14

01 Apr 2006 7:16 verilog concatenate string

hi davyzhu,
You can use $swrite to do what you want or use the attach file that I had implement C-like string manipulation function in verilog task.

Sincerely,
Jarod

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