| Author |
Message |
param
Joined: 09 Sep 2005 Posts: 46 Helped: 4
|
10 Mar 2006 10:25 verilog fread |
|
|
|
|
hi all,
how to assign the input data written in a file to the port, for testbench purpose using verilog hdl?
suppose i have some samples of input data written in .dat file,
and in my testbench i want to input all the values written in that file, how can i do it?
i have tried in the below manner and could not find any data assigned to the input pin while simulating,
data_in = $fopen('' input.dat","r");
please help to solve this.........
|
|
| Back to top |
|
 |
vivek
Joined: 19 May 2005 Posts: 69 Helped: 9
|
10 Mar 2006 11:21 verilog read file |
|
|
|
|
$fopen will only open the file. To do any file operation in verilog this has to be done first. for reading from file try $memreadb (for binary files) or $memreadh (for hex files).
eg :
| Code: |
reg [7:0] mem[1027:0];
......
initial
begin
$readmemb("file_name",mem);
end |
U also have $fscanf, $fgetc, $fread to read files. Not sure abt the exact syntax for their usage, but should be similar to above one.
|
|
| Back to top |
|
 |
darylz
Joined: 24 Mar 2005 Posts: 132 Helped: 4
|
10 Mar 2006 12:33 verilog read from file |
|
|
|
|
| system command
|
|
| Back to top |
|
 |
nand_gates
Joined: 19 Jul 2004 Posts: 907 Helped: 120
|
10 Mar 2006 13:12 verilog file read |
|
|
|
|
Here is the example ur looking for .....
Hope this helps
| Code: |
module stim_gen (
// Outputs
clk, data
);
output clk;
output [7:0] data;
reg clk;
reg [7:0] data;
integer fd;
integer code, dummy;
reg [8*10:1] str;
initial begin
fd = $fopen("_input.dat","r");
clk = 0;
data = 0;
code = 1;
$monitor("data = %x", data);
while (code) begin
code = $fgets(str, fd);
dummy = $sscanf(str, "%x", data);
@(posedge clk);
end
$finish;
end // initial begin
always #5 clk = ~clk;
endmodule // stim_gen |
Contents of _input.dat file
| Code: |
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
|
|
|
| Back to top |
|
 |
Google AdSense

|
10 Mar 2006 13:12 Ads |
|
|
|
|
|
|
| Back to top |
|
 |
banjo
Joined: 24 Dec 2005 Posts: 644 Helped: 118
|
10 Mar 2006 13:58 reading a file in verilog |
|
|
|
|
FYI,
If you want to process binary data, this can be tricky readmemb did not work for me when I needed to do this. I finally ended up using:
file = $fopen("code.vec", "r");
return_value = $fread( mem, file);
if (return_value !=1)
error = 1;
else
..............
"mem" is an eight bit varible. When the return_value is not 1, then the read failed and you are at the end of the file.
--- Steve
|
|
| Back to top |
|
 |