| Author |
Message |
ne.me.sis
Joined: 25 Feb 2006
Posts: 13
|
 01 Mar 2006 6:58 problem with vcd file |
|
|
|
Hello. Would like to know the common ways(or eda tools) that are used to estimate power for IC, both digital and analog. Can it be done for gated clock design? How is the accuracy? Please share your experiences and thoughts. Thanks.
Last edited by ne.me.sis on 30 May 2006 4:06; edited 1 time in total |
|
| Back to top |
|
 |
Garbielhijo
Joined: 27 Feb 2006
Posts: 9
Helped: 1
|
| 01 Mar 2006 7:22 Re: power estimation |
|
|
|
| I use a littler bit of Astro Rail for power analysis, is good for this task but I used it just for digital analysis. All the analog section was implemented as a hard macro with a model for the power and switching.
|
|
| Back to top |
|
|
stevepre
Joined: 10 May 2001
Posts: 90
|
| 01 Mar 2006 8:37 Re: power estimation |
|
|
|
Use gatelevel simulation on post-P&R netlist.
The result is very close to lab data.
|
|
| Back to top |
|
|
ne.me.sis
Joined: 25 Feb 2006
Posts: 13
|
| 01 Mar 2006 8:47 Re: power estimation |
|
|
|
Hello Garbielhijo, can you elaborate a little bit more on power analysis with astro rail. What are the inputs that it take in and what are the outputs?
Hello stevepre, how do you extract the power data from post P&R simulation? I don't get you.
Actually, I never do power estimation for my chip before, but right now I am looking for a method so that I can have better control of the power comsumption. Therefore, please explain more when you chip in your comments/ideas. Thanks.
|
|
| Back to top |
|
|
stevepre
Joined: 10 May 2001
Posts: 90
|
| 01 Mar 2006 9:31 Re: power estimation |
|
|
|
Using any backend flow is going to take a long long time. Not practical.
Using any RTL power estimation is way off reality.
Using gatelevel simulation (after P&R gate, so the clock tree is there).
Basically, the flow is: you prepare the gatelevel netlist, get SDF from backend people as well as parasitic information (the cap and resistor) file from backend people as well.
Option 1: Run gatelevel simulation with SDF, dump VCD ==> well...the size of VCD easily goes beyond 4G, so....you have to control your simulation time and positiion very well.
Option 2: similiar to option 1, but dump FSDB file. Synopsys primepower can read in streaming FSDB file and calculate the power.
Option 3: run gatelevel simulation, but link the PLI to dump SAIF file instead of VCD or FSDB.
Calculate the power from either one of the above 3 options with primepower.
but with option 3, you won't get power-vs-time chart. But you get one number over your simulation period. But it's as accurate as others (over that period of time)
|
|
| Back to top |
|
|
pandit_vlsi
Joined: 15 Feb 2006
Posts: 63
Helped: 2
Location: b'lore,india
|
| 01 Mar 2006 9:46 Re: power estimation |
|
|
|
hi.
power can be estimated right from rtl to post layout.as size of the chips is decreasing...so powr estimation is beginning right from rtl.
there is prime theatretool to get power at rtl level,prime power tool at netlist,astrorail&blast rail ,redhawk at post layout level.
i used redhawk at post layout for both static&dynamic ir drop analysis.
...
pandit
|
|
| Back to top |
|
|
jcchan
Joined: 28 Apr 2005
Posts: 33
Helped: 1
|
| 03 Mar 2006 3:47 Re: power estimation |
|
|
|
| power can be estimated from the cell toggle so designer know the total cell toggle rate in normal function to estimate the all transaction current in clock rising or falling then to decide the power ring width.
|
|
| Back to top |
|
|
jzhangsun
Joined: 05 Mar 2006
Posts: 13
|
| 05 Mar 2006 4:18 power estimation |
|
|
|
hi pandit_vlsi
i am interesting in power analysis tool at RTL level,would you like tell me the typical tool that
is available now.
|
|
| Back to top |
|
|
stevepre
Joined: 10 May 2001
Posts: 90
|
| 07 Mar 2006 3:30 Re: power estimation |
|
|
|
| sequence design, powertheater
|
|
| Back to top |
|
|
ne.me.sis
Joined: 25 Feb 2006
Posts: 13
|
| 30 May 2006 4:04 Re: power estimation |
|
|
|
Anyone run power estimation with vcd file before? I received warnings that nets are not covered by VCD file and an error,"Error: (read_vcd) Strip path can not be matched in the VCD file.
What I did are:
1) In testbech,
initial
begin
$dumpfile("top.vcd");
$dumpvar("0,top");
end
2) Run sim and obtain top.vcd
3) Read in gate netlist, spef file and vcd file in prime power.
Anything wrong with my steps? How should I verify those nets are in the vcd file?
Another question is how to clip the time so that we can get an accurate vcd for power calculation? Doing it manually after getting the vcd file or there is other ways to do so?
I noticed that the vcd file can easily become very large. How to handle and manage the vcd file? I read an article in solvenet, where we can split the vcd file. Anyone has tried before?
Thanks.
|
|
| Back to top |
|
|
manu_leo
Joined: 01 Dec 2005
Posts: 41
Location: bangalore
|
| 30 May 2006 10:24 Re: problem with vcd file |
|
|
|
if ur using powertheater use -mixed option rather than full simulation one.
Basically the tool searches for all the nets toggle information from vcd file, if that is not there gives out wn error. If u use -mixed option, it will do probablistic estimation.
|
|
| Back to top |
|
|
tinu90
Joined: 24 Jun 2006
Posts: 3
|
| 24 Jun 2006 7:03 Re: power estimation |
|
|
|
| ne.me.sis wrote: |
Anyone run power estimation with vcd file before? I received warnings that nets are not covered by VCD file and an error,"Error: (read_vcd) Strip path can not be matched in the VCD file.
What I did are:
1) In testbech,
initial
begin
$dumpfile("top.vcd");
$dumpvar("0,top");
end
2) Run sim and obtain top.vcd
3) Read in gate netlist, spef file and vcd file in prime power.
Anything wrong with my steps? How should I verify those nets are in the vcd file?
Another question is how to clip the time so that we can get an accurate vcd for power calculation? Doing it manually after getting the vcd file or there is other ways to do so?
I noticed that the vcd file can easily become very large. How to handle and manage the vcd file? I read an article in solvenet, where we can split the vcd file. Anyone has tried before?
Thanks. |
1. Try dumping VCDs at partition level and not Full Chip
2. initial
begin
$dumpfile("top.vcd");
$dumpvar("0,top"); <----Not sure if this is effective. Try "vcd add -r hierarchy/*"
end
3. I assume you are using MODELSIM for your simulations
try this
vcd file dummy_vcd.vcd
vcd add -r hierarchy/*
4.
Anything wrong with my steps? How should I verify those nets are in the vcd file?
When you run the PP tool, look for VCD annotaion. This is a good indicator as to how the annotation occurs
|
|
| Back to top |
|
|
