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bracketx
Joined: 11 Jan 2006
Posts: 12
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 21 Feb 2006 9:54 Is ADPLL's jitter related to the frequency of PLL? |
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| If the control of ADPLL is according to the counter, low frequency means a bad jitter. Is that true?
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rfsystem
Joined: 25 Feb 2002
Posts: 798
Helped: 85
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| 21 Feb 2006 10:18 Re: Is ADPLL's jitter related to the frequency of PLL? |
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Did you mean low comparison frequency? If the frequency control is digital there is no difference to a time discrete value continiuous control. The problems are in the detail:
1. Digital control with high resolution is often nonmonotonic or has to use multiple segments.
2. Phase resolution requires to count at very high frequencies. In a analog PLL you get some ps resolution (noise limit)
Try to calculate the noise performance of your complete digital ADPLL. Then you know how many bits you need there.
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bracketx
Joined: 11 Jan 2006
Posts: 12
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| 25 Feb 2006 10:10 Is ADPLL's jitter related to the frequency of PLL? |
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| what's the multiple segments?Do you mean that ADPLL is not suitable for low time jitter PLL design?
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