How to implement Built In Self Test for RAM using verilog

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writetoknitin

Joined: 12 Feb 2006
Posts: 1

12 Feb 2006 15:20 implement memory verilog

Provided a verilog code is available for a RAM , how to go about writing a BIST code for the RAM.

funzero

Joined: 19 Nov 2004
Posts: 204
Helped: 8

13 Feb 2006 13:09 how to implement ram in verilog

I know SRAM has some standard test algrithm . pls search google for this.
you can choose one to use.
and then implement it in RTL , do not forget to use a MUX to indicate a normal mode and a bist mode .

linuxluo

Joined: 26 Jul 2002
Posts: 516
Helped: 4

13 Feb 2006 16:08 sram bist verilog

hi,
you have two ways :
1. using membist from mentor to do it , this tool is easy to use
2. find ip on opencore site.

zhustudio

Joined: 15 Jul 2002
Posts: 104
Helped: 6
Location: China

14 Feb 2006 8:52 sram bist verilog code

Mentor Mbistarchitecture is powerful tools to give memory bist logic in RTL format. It is readable.
You can design memory BIST circuit by a LFSR and PREG, It is two FSM. You can see any DFT book.
And you can refer synopsys DW_rambist about the memory bist arch.

For test algorithm and fault model, please search in IEEE or google. There are lots paper to say that.

Or you can see the book
Essentials of Electronic Testing for Digital, Memory, and Mixed-Signal Vlsi Circuits
by Michael J Bushnell, Vishwani D Agrawal

satya_422

Joined: 27 Sep 2006
Posts: 74
Helped: 4

30 Jul 2007 9:31 bist ram verilog

i hope BIST is generated using the tool you need not do manually

just go through the process guide of mbistarchitect

writetoknitin wrote:

Provided a verilog code is available for a RAM , how to go about writing a BIST code for the RAM.

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satya_422

Joined: 27 Sep 2006
Posts: 74
Helped: 4

01 Aug 2007 6:08 sram tester verilog

1)the bist controller is generated by giving the memeory model as an input to the mbistarchitect tool
2)it generates bist controller,bist connection and testbench fiels.
3)now simulate this 3 files and the memory if test passes then its good if it fails just debug it.