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Relation betweek low Vt and leakage?

 
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singu31



Joined: 22 Dec 2005
Posts: 10
Post11 Feb 2006 4:00   Relation betweek low Vt and leakage?
Hi,

I went through a couple of papers on Multiple Vt CMOS structures for low power design. In all of these they say that scaling down supply voltage reduces power consumption as

Power α (VDD)^2.

But as we scale down supply voltage we also have to scale down Vt.

I dont understand exactly why the leakage current increases as we scale down Vt? Why do high Vt transistors have lesser leakage than Low Vt transistors?

Please clarify.

Thanks

Singaravelan
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v_c



Joined: 11 Oct 2005
Posts: 467
Helped: 84
Post11 Feb 2006 4:40   Re: Relation betweek low Vt and leakage?
I think what you are dealing with here is the increase in leakage due to sub-threshold operation. I recently posted an answer to a very similar question
on the board in the "Analog Circuit Design" section. Here's the link

http://www.edaboard.com/viewtopic.php?t=153275&highlight=

I hope this helps you out.

Best regards,
v_c
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