What's NCVerilog Snapshot mean?

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davyzhu

Joined: 23 May 2004
Posts: 521
Helped: 3
Location: oriental

10 Feb 2006 15:21 ncsim tutorial

Hi all,

I used to be a Modelsim user. Now my boss force me to use NCVerilog(seems very difficult to learn). We dump data from NCVerilog and view signal using Debussy. All controled by script.

What's Snapshot mean in NCVerilog?

BTW, may you recommend some tutorial on NCVerilog?

Best regards,
Davy

aji_vlsi

Joined: 10 Sep 2004
Posts: 640
Helped: 72
Location: Bangalore, India

10 Feb 2006 16:57 simvision snapshot

davyzhu wrote:

Hi all,

I used to be a Modelsim user. Now my boss force me to use NCVerilog(seems very difficult to learn).

A change is always hard to adopt to, but that's the only thing that remains "unchanged" Smile

Quote:

We dump data from NCVerilog and view signal using Debussy. All controled by script.

Interesting, if you are OK - may I ask you what's that you find so good about Debussy? I know Waveform/Debug tools are very very personal favorite things hence once used to it, no body feels like changing. Besides the look-and-feel, do you see any potential benefit of Debussy over Simvison (part of ncsim)? Any advanced debug features that you just can't live without and that simvision doesn't have it? I used Simvision few years ago, and was amazed by it - was quite good.

Quote:

What's Snapshot mean in NCVerilog?

I believe this name/concept came from NCVHDL. VHDL LRM has compile-elaborate-simulate steps well explained. It says at the end of elab stage one gets a simulatable model ready to start form time 0. NC names such a "read-to-simulate" model as Snapshot.

Quote:

BTW, may you recommend some tutorial on NCVerilog?

Best regards,
Davy

Perhaps some google might hep you. But I can offer basic help on a case to case basis, so feel free to post queries such as:
This is how I do it in MTI, how do I do that in NC. I *might* be able to help.

Good Luck
Ajeetha, CVC
www.noveldv.com

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10 Feb 2006 16:57 Ads

kgeorge123

Joined: 23 Mar 2005
Posts: 34
Helped: 6

10 Feb 2006 20:30 ncsim snapshot

There are various steps while you are using NCVerlilog in the Cadence tool.
After writing RTL you need to elaborate the design to create a snapshot.

The elaborated design hierarchy is stored in a simulation snapshot, which is the representation of your design that the simulator uses to run the simulation. The snapshot is stored in the library database file along with the other intermediate objects generated by the compiler and elaborate.

The advantage here is fast simulations times compared to other toos like Mentor once.
This helps when you are running really big designs.
Debussy is a wonderful tool to do lot of debugging once you have the final netlist ready.

Attached is the NClauch tutorial which is a GUI tool for running NCverlilog or NCVHDL

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carrot

Joined: 23 Feb 2004
Posts: 173
Helped: 3
Location: Bangalore, India

11 Feb 2006 7:57 ncverilog snapshot

Hi,

Once you have elaborated the design testbench, the ouutpt of elaboration is in the form of SSS file, which is refered to as snapshot.
Snapshot is the one which you load the elaborated file into the simulator - ncsim.

davyzhu

Joined: 23 May 2004
Posts: 521
Helped: 3
Location: oriental

12 Feb 2006 3:12 ncverilog debussy

Hi all,

Thank you for your help!

A more question: can I use NCLaunch to replace the script control?

Or can NCLaunch do all the possible simulation work?

Best regards,
Davy

funzero

Joined: 19 Nov 2004
Posts: 204
Helped: 8

13 Feb 2006 13:13 ncverilog tutorial

In my opinion , the NC snapshot just a picture of the simulation environment .
the sim run from time 0 to finish time .each time step , will freeze to do follow thing . evaluate schedule update segment . the freeze scene is the snapshot.

linuxluo

Joined: 26 Jul 2002
Posts: 516
Helped: 4

13 Feb 2006 16:06 cadence nc verilog snapshot

hi, davyzhu
mostly you can use nclauch to do script job, but I thik script is a good start for using eda tools.
btw: ncsim is most powerful simulation tool in eda world