FSM - finite state machine

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elecs_gene

Joined: 20 Dec 2005
Posts: 48
Helped: 2

05 Feb 2006 6:40 FSM - finite state machine

hi guys,
could u please help me in developing the state machine for detecting multiples of 5..that is output is 1 if any multiple of 5 is detected..the input comes serially..after the each input,you have to store it in some sort of infinite register and check for multiple of 5..

mukund

Davood Amerion

Joined: 01 Mar 2005
Posts: 589
Helped: 90
Location: Persia

05 Feb 2006 10:50 FSM - finite state machine

can you explain about input words format . is it integer, binary, bcd, 2 digit, n digit?

elecs_gene

Joined: 20 Dec 2005
Posts: 48
Helped: 2

05 Feb 2006 11:08 Re: FSM - finite state machine

the input is binary..the actual problem is that multiples of 5 don't follow a pattern such as---101 for 5,1010 for 10,1111 for 15 etc....that is the problem..

with regards

jearome

Joined: 01 Sep 2005
Posts: 212

06 Feb 2006 2:09 Re: FSM - finite state machine

I think you should use division operation

elecs_gene

Joined: 20 Dec 2005
Posts: 48
Helped: 2

10 Feb 2006 19:15 Re: FSM - finite state machine

hi
if u say u have to use division,how can u implement it using an fsm??moreover,it should be good enough to detect any multiple of 5..

regards

tkbits

Joined: 04 Dec 2004
Posts: 235
Helped: 36

11 Feb 2006 2:05 Re: FSM - finite state machine

If your input is bit serial with MSB first, then you can check if the current bit string you have received is divisible by 5.

I don't know how you can check the divisibility using only the bit pattern. If you add a subtraction unit and a register, the state machine will be simple. You will need a separate condition to indicate when you have reached the end of the number.

noloser

Joined: 21 Jan 2006
Posts: 17
Location: Singapore

11 Feb 2006 8:47 FSM - finite state machine

is it die die must be model in FSM? this shall be much easier if you model in behaviour mode. just capture the serial input, convert it to integer and check for the value mod 5 equal to 0 will do the work.

OvErFlO

Joined: 07 Dec 2001
Posts: 308
Helped: 3

12 Feb 2006 15:33 Re: FSM - finite state machine

I think that the better solution is an infinity ROM... if you can't find periodicity in the number multiply of 5.

in the second use a Divider unit... but if you need speed it isn't a better solution...

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Hero

Joined: 06 Mar 2002
Posts: 145
Helped: 2

28 Feb 2006 5:53 Re: FSM - finite state machine

Yes

I think that ROM is better solution than FSM or arithmetical unit. You need to generate appropriate ROM table and directly detect multiples of five. For 8-bit input data you need only 256 bytes of memory. Connect input data bus to ROM address bus and use ROM output bus for detection.

verilog_coder

Joined: 04 Jan 2006
Posts: 68
Helped: 6
Location: Pakistan

28 Feb 2006 14:44 FSM - finite state machine

I have one scheme in mind.it is something like it. You need to have your own buffer to compare the incoming stream . I am assuming the stream is coming with lsb arriving first. now initially store the value 5 in your buffer say temp buffer.

if temp buffer is equal to stream buffer.
{
set divide by 5 output high.
increase temp buffer by 5.
}
else if{
stream buffer value is greater than temp buffer
{
increase temp buffer by 5.
set divide by 5 output low.
}
else
{
temp buffer retains its value.
set divide by 5 output low.
}

nand_gates

Joined: 19 Jul 2004
Posts: 907
Helped: 120

10 Apr 2006 14:12 Re: FSM - finite state machine

Here goes the solution!
The idea here is we need to convert the infinite bin no. to BCD we should only
look for BCD LSB if it is 0 or 5 the no. is divisible by 5!
Rest the code will explain!
Hope this helps

Quote:

module div5(
// Outputs
y,
// Inputs
clk, reset_n, d
);
input clk, reset_n;
input d;
output y;

reg [3:0] q_reg;
reg [3:0] q_reg_nx;

assign y = (q_reg == 5) || (q_reg == 0);

always @(posedge clk or negedge reset_n)
if (!reset_n)
q_reg <= 0;
else
q_reg <= q_reg_nx;

always @(d or q_reg) begin //shift and decimal adjust the lsb
q_reg_nx = {q_reg[2:0], d};
if (q_reg_nx > 9 || q_reg[3])
q_reg_nx = {q_reg[2:0], d} + 6;
end
endmodule // div5