electronics forum

Rules | Recent posts | topic RSS | Search | Register  | Log in

System Verilog in Magma
Post new topic  Reply to topic    EDAboard.com Forum Index -> ASIC Design Methodologies & Tools (Digital) -> System Verilog in Magma
Author Message
hyy95120



Joined: 21 Oct 2005
Posts: 36
Post29 Jan 2006 23:15   

System Verilog in Magma
hi,
How can I import system verilog code in blastcreate?

using

import rtl xxx.v

report error message

On magma's web site, it said

"...Blast Create accepts RTL (Verilog, System Verilog or VHDL) or netlist input ..."

But I can't find any info from the online documents.


Please help!

Thanks!
Back to top
kbulusu



Joined: 23 Apr 2003
Posts: 133
Helped: 7
Post31 Jan 2006 2:26   

Re: System Verilog in Magma
only new versions/builds released in Jan support SV and also they can just parse..they wont infer any logic..also they are supporting only assertions as of now...hope this helps...
Back to top
spauls



Joined: 17 Dec 2002
Posts: 547
Helped: 19
Post31 Jan 2006 6:34   

Re: System Verilog in Magma
No you cant do for System verilog
Back to top
aji_vlsi



Joined: 10 Sep 2004
Posts: 640
Helped: 72
Location: Bangalore, India
Post01 Feb 2006 15:17   

Re: System Verilog in Magma
kbulusu wrote:
only new versions/builds released in Jan support SV and also they can just parse..they wont infer any logic..also they are supporting only assertions as of now...hope this helps...

Hi,
Does Magma support assertions for Synthesis? What does it synthesize to? I know DC "ignores" them - so simply parsing doesn't mean it "supports" it.

Regards
Ajeetha, CVC
www.noveldv.com
Back to top
spauls



Joined: 17 Dec 2002
Posts: 547
Helped: 19
Post02 Feb 2006 7:30   

Re: System Verilog in Magma
Ajeetha ,
Magma also has some special switches for synthesis off for particular lines.
Assertions are very well defined under that sections.
Back to top
Google
AdSense
Google Adsense
Post02 Feb 2006 7:30   

Ads


Back to top
aji_vlsi



Joined: 10 Sep 2004
Posts: 640
Helped: 72
Location: Bangalore, India
Post02 Feb 2006 9:55   

Re: System Verilog in Magma
spauls wrote:
Ajeetha ,
Magma also has some special switches for synthesis off for particular lines.
Assertions are very well defined under that sections.

Hi,
So you are saying that if my assertions are inside "pragma"s (such as translate_on/off) - then Magma can handle it - that makes sense, in that case it simply doesn't even see that code.

Thanks
Ajeetha, CVC
Back to top
kbulusu



Joined: 23 Apr 2003
Posts: 133
Helped: 7
Post03 Feb 2006 0:21   

Re: System Verilog in Magma
Ajeetha,
As I mentioned earlier..it doesnt synthesize to anything...EDA vendors normally add "support" in phases depending on the interests of customers...Right now, majority of the customers only use assertions and most of the designers and design managers whom I talk to are still reluctant to write synthesizable code in SV for variety of reasons...number one is most design houses want all their EDA vendors to be on the same level...since designers are using assertions for DV purposes ..it makes sense for EDA tool vendors atleast to have assertions support initially sothat they wont choke when it sees SV constructs...I hope this helps...ur book coauthored with Ben is good..

cheers kiran.

[quote="aji_vlsi"][quote="kbulusu"]only new versions/builds released in Jan support SV and also they can just parse..they wont infer any logic..also they are supporting only assertions as of now...hope this helps...[/quote]
Hi,
Does Magma support assertions for Synthesis? What does it synthesize to? I know DC "ignores" them - so simply parsing doesn't mean it "supports" it.

Regards
Ajeetha, CVC
www.noveldv.com[/quote]

[size=9][color=#999999]Added after 1 minutes:[/color][/size]

yes magma can handle non propietary synopsys stuff...said that it can handle synopsys translate_off/on ...

[quote="aji_vlsi"][quote="spauls"]Ajeetha ,
Magma also has some special switches for synthesis off for particular lines.
Assertions are very well defined under that sections.[/quote]
Hi,
So you are saying that if my assertions are inside "pragma"s (such as translate_on/off) - then Magma can handle it - that makes sense, in that case it simply doesn't even see that code.

Thanks
Ajeetha, CVC[/quote]
Back to top
Arabic versionBulgarian versionCatalan versionCzech versionDanish versionGerman versionGreek versionEnglish versionSpanish versionFinnish versionFrench versionHindi versionCroatian versionIndonesian versionItalian versionHebrew versionJapanese versionKorean versionLithuanian versionLatvian versionDutch versionNorwegian versionPolish versionPortuguese versionRomanian versionRussian versionSlovak versionSlovenian versionSerbian versionSwedish versionTagalog versionUkrainian versionVietnamese versionChinese version
Post new topic  Reply to topic    EDAboard.com Forum Index -> ASIC Design Methodologies & Tools (Digital) -> System Verilog in Magma
Page 1 of 1 All times are GMT + 1 Hour
Similar topics:
System Verilog and System Verilog Assertions Tutorial (1)
Comparison of VHDL, Verilog, and System verilog (2)
Advantage of System C over System Verilog (2)
system verilog & verilog (2)
System C, System verilog, or Vera (11)
System C & system Verilog (9)
System Verilog (1)
system verilog (18)
system verilog? (2)
system verilog (1)


Abuse || Administrator || Moderators || Support us || sitemap
topic RSS