Synthesis Help:in verilog codes

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aravind

Joined: 29 Jun 2004
Posts: 622
Helped: 23
Location: india

28 Jan 2006 4:12 Synthesis Help:in verilog codes

Hi friends
i written one matrix multication codes using $readmemb command (reading from file.txt) .how synthesis this code?

howto write verilog code for same matrix inside of file.txt in Mem LUT or ROM.

please help me .
take same matrix multi code like 3X3 with 1X3 in verilog and reply soon
thanks

moneychaser

Joined: 28 Aug 2004
Posts: 20

28 Jan 2006 19:47 Synthesis Help:in verilog codes

$readmemb is only synthesizable with Synplify. No other tool will synthesize it as far as I know.

anjali

Joined: 16 Aug 2005
Posts: 174
Helped: 8

29 Jan 2006 12:39 Re: Synthesis Help:in verilog codes

first, have a verilog code for multiplier with i/p & o/p ports. synthesize it. then have a top level environment which passes ips from the ips.txt ( can use $readmemb ) to the netlist.

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jarhaur

Joined: 01 Feb 2006
Posts: 6

02 Feb 2006 7:58 Synthesis Help:in verilog codes

Hi

The $readmemb task is not synthesisable coding.
The synthesis tool only supports RTL coding stlye but behavior coding. The behavior coding style is high level describation that is using at the verification stage.

If you wants to have a storage with default value, you may implement it by FF with asynchronus reset/set. After the reset is released, the storage will have the diresed default.

If your design is completed by the FPGA, you may use the internal ROM.

http://toolbox.xilinx.com/docsan/data/alliance/pft/pft2_4.htm

zhustudio

Joined: 15 Jul 2002
Posts: 104
Helped: 6
Location: China

02 Feb 2006 13:45 Synthesis Help:in verilog codes

There are two ways to implement your design without $readmemb.
1. Use ROM to store the matrix value and read out each value at specific address. It will need a Memory Compiler from Asic library foundry or IP from FPGA vendor. You can use Artisan memory compiler or Xillinx Coregen to generate ROM instant and give the ROM value in your txt file.
2. Use TieHi and TieLow cell to give a constant value. It will save more area than DFFs. And it will easy to be modified in Metal-edit stage in final ECO.

$readmemb can not be synthesized in common tools. So use above methods.

Good Luck Smile

aravind

Joined: 29 Jun 2004
Posts: 622
Helped: 23
Location: india

02 Feb 2006 14:45 Synthesis Help:in verilog codes

hi zhustudio
that answer im expecting . u clear me .
by i need an examples program of rom and how to import the data from rom to ram and how to portmap it.
simple example clear me more

zhustudio

Joined: 15 Jul 2002
Posts: 104
Helped: 6
Location: China

02 Feb 2006 16:00 Synthesis Help:in verilog codes

Hi aravind,
I does not have more general tutorial of ROM instance. For ASIC design, different Memory Compiler have different usage. But commonly, you will be asked to provide ROM file (txt file) to the memory compiler and it will give out simulation model, liberty, lef and GDSII files.

For FPGA, usage of Coregen, Xilinx. You can view the help. It is simple.

And you want to import data from ROM to RAM?
what does your mean? Can you describe it clearly?
I am sorry for my understanding.

aravind

Joined: 29 Jun 2004
Posts: 622
Helped: 23
Location: india

02 Feb 2006 23:39 Synthesis Help:in verilog codes

yes correct . i wanna import data from ROM to RAM.
because ROM is inside/or outside the chip. i wanna import it to RAM .and access that data from RAM.
how instancitate it. how to write code for that.
thanks