An advice about glitch

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OvErFlO

Joined: 07 Dec 2001
Posts: 308
Helped: 3

20 Dec 2005 3:31 An advice about glitch

I have a FPGA Xilinx that generate a 20 Mhz clock (sclk) for drive a DAC, now when I trasmit serial data (sdata) from controller to DAC, DAC acquire serial datas on falling edge and on rising edge I observe glitch (I have see on modelsim simulation), the question is :

If I receive a glitch on rising edge, it's possible that my signal on falling edge can't obtain VIL or VOH to identify a 0 or a 1 ???

What can I do to avoid this ?

thanks

Iouri

Joined: 17 Aug 2005
Posts: 687
Helped: 79

22 Dec 2005 21:50 An advice about glitch

did you see glitch on the "real" hardware?

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Resistance

Joined: 24 Dec 2005
Posts: 77
Helped: 3

25 Dec 2005 11:37 Re: An advice about glitch

Hi,

First am not clear with the q i will reply with wat i undersatood.

glitches result when there is race condition or skew but on thing dude glitch can trigger the circuit and can take it on a metasatble state ride..

so it would be helpful if u get to root of the prob or explain i will try..

regards

tkbits

Joined: 04 Dec 2004
Posts: 235
Helped: 36

26 Dec 2005 2:02 Re: An advice about glitch

A glitch is detrimental if it's on a clocking signal, as that can create an extra, unwanted clock period.

If it's on a "data" signal, it will be ignored if it occurs after the capturing clock edge, and it is stable long enough (satisfies setup time) before the next capturing clock edge.