how to make my design as black box

EDAboard.com Forum Index -> ASIC Design Methodologies & Tools (Digital) -> how to make my design as black box

Author

Message

aravind

Joined: 29 Jun 2004
Posts: 622
Helped: 23
Location: india

08 Dec 2005 4:31 how to make my design as black box

hi friends
how i create my own black box module

example for an equalizer i need fir filter.
i wanna create fir filter module as a black box.
i synthesis and got the netlist . and efficiently place and route it.
in backend i dont wanna change place of cells in my FIR filter.
for that what i do.

tarkyss

Joined: 01 Aug 2005
Posts: 342
Helped: 16
Location: China

08 Dec 2005 4:53 how to make my design as black box

BPV extract in Astra or Milkyway
you can reference Milkyway reference in detail

ami

Joined: 28 Apr 2005
Posts: 62
Helped: 4
Location: VN

08 Dec 2005 5:03 Re: how to make my design as black box

Just build a tool (Perl-script for an example). This tool will search the module inyour netlist file, remove all logic in that module ( except the module declaration, input,output,output) ----> it will be a black box.
Then, after your process - this tool will re-insert the removed code into that module.
Regards

aravind

Joined: 29 Jun 2004
Posts: 622
Helped: 23
Location: india

08 Dec 2005 5:06 how to make my design as black box

i dont know perl script . can u give small example script and papers

ami

Joined: 28 Apr 2005
Posts: 62
Helped: 4
Location: VN

08 Dec 2005 5:34 Re: how to make my design as black box

Just use this code. You can find many Perl-script materials from internet.
This is a sample script ( create black_box in netlist)

Code:

#!/usr/bin/perl

$file_name = $ARGV[0]; #source file name
$file_name1= $ARGV[1];#destination file name
$source_path = "/netlist/";
$dest_path = "/netlist/";
$read_file_name = $source_path.$file_name;
$write_file_name =$dest_path.$file_name1;
$write_file_name2 =$dest_path."output.netlist";
$write_file_name3 =$dest_path."output1.netlist";
$search_str = "your_module_name_to_create_black_box"
#########################################################################################
select STDOUT;
open(read_file,"$read_file_name") || die "can not open file $read_file_name\n";
@list = {};
@a = {};
$m_a = 0;

@b = {};
$m_b = 0;

@c = {};
$m_c = 0;

@d = {};
$m_d = 0;
$c = 0;
$k = 0;
$k1 = 0;

#Split area for del core

while (<read_file>)
{
chop;
@list[$c] = "$_";
if (index(@list[$c],$search_str) != -1)    {$k = 1;}
if (($k == 1)and (index(@list[$c],"endmodule")!= -1)) {$k = 0;}
if (($k == 1)and (index(@list[$c],"wire")!= -1)) {$k1 = 1;$pont1 =$c; printf "\n$pont1 $search_str";}
if (($k1 == 1)and (index(@list[$c],"endmodule")!= -1)){$k1 = 0;$pont2 = $c;printf "\n$pont2";}
if (($k == 1)and ($k1 == 0)) {@b[$m_b] = @list[$c];$m_b++;}
if ($k1 == 0) {@a[$m_a] = @list[$c]; $c++; $m_a++;}
else {$c++;}
}

$j=0;
$tam = 0;
$tam2 = 0;
printf "\n m_b=$m_b";
while ($j <$m_b)
{
if((index(@b[$j],"output")!= -1) and (index(@b[$j],";") !=-1) and (index(@b[$j],",") ==-1) )
{
$length = length(@b[$j]);printf "\nLength = $length\n";
$length1 = rindex(@b[$j]," "); printf "\nLength1 = $length1\n";
$sub_str = substr(@b[$j],$length1,$length-$length1-1);
@c[$m_c] = $sub_str;
$m_c++;
}
if((index(@b[$j],"output")!= -1) and (index(@b[$j],",") !=-1)) { $tam = 1;$tam2 = 1;} else {$tam2 =0;}
if (($tam == 1) and ($tam2 == 1)) {@d[$m_d] = substr(@b[$j],9,length(@b[$j])+1);$m_d++}
if (($tam == 1) and ($tam2 == 0)) {@d[$m_d] = substr(@b[$j],9,length(@b[$j])+1);$m_d++}

$j++;
}
close (read_file);

#////////////
$j=0;
$str ="";
while ($j<$m_d)
{
$str = $str.$d[$j];
$j++;
}
$length_str = length($str);
$str = substr($str,0,$length_str-1);
@split_array = split(/,/,$str);
$count_array = @split_array;
@c1 = (@c,@split_array);
$m_c1 = @c1;

#///////////////////////////////////
$j=0;
$a_str = "assign ";
while ($j <$m_c1)
{
$stra = @c1[$j];
@c1[$j]= $a_str.$stra." = 0;";
$j++;
}
#////////////////////////////////////
$j = 0;
$j1 =0;
open(write_file,">$write_file_name") || die "can not open file $write_file_name\n";
open(read_file,"$read_file_name") || die "can not open file $read_file_name\n";
while( <read_file> )
      {
      chop;
      select write_file;
      if ($j == $pont1) {last;}
      print "$_\n";
      $j++;
      }
$i = 0;
while($i < $m_c1)
{
   printf "@c1[$i]\n";
   $i++;
}
printf "endmodule\n";
while( <read_file> )
      {
      chop;
      #select write_file;
      if ($j >= $pont2)
         {
      print "$_\n";
      }
      $j++;
      }
close(read_file);
close(write_file);
printf "\n";

Hope this help

Last edited by ami on 09 Dec 2005 4:07; edited 1 time in total

jcchan

Joined: 28 Apr 2005
Posts: 33
Helped: 1

09 Dec 2005 3:11 Re: how to make my design as black box

You cna try this verilog example and the synthesis tools will make the module to be black box.

modue test (in1, in2,in3, out3);
input in1, in2, in3;
output out3;
//synopsys translate_off
assign out3 = in1 | in2 | in3;
//synopsys translate_on
endmodule

aravind

Joined: 29 Jun 2004
Posts: 622
Helped: 23
Location: india

09 Dec 2005 3:16 how to make my design as black box

can u give more information about how to proceed with block

farmerwang

Joined: 29 May 2002
Posts: 60
Helped: 1

09 Dec 2005 6:32 Re: how to make my design as black box

Don't understand what do you mean by black box your design. Do you mean to protect your design from being read by other people?

aravind

Joined: 29 Jun 2004
Posts: 622
Helped: 23
Location: india

23 Dec 2005 14:59 how to make my design as black box

my aim is P&R tools shouldnt touch my blockbox. for placement and routing.

brotherjam

Joined: 10 Dec 2005
Posts: 7
Helped: 1

24 Dec 2005 3:34 how to make my design as black box

modue test (in1, in2,in3, out3);
input in1, in2, in3;
output out3;
//synopsys black_box
//(you can find it in DC manual)
//synopsys translate_off
assign out3 = in1 | in2 | in3;
//synopsys translate_on
endmodule

Google
AdSense
Google Adsense

24 Dec 2005 3:34 Ads

aravind

Joined: 29 Jun 2004
Posts: 622
Helped: 23
Location: india

24 Dec 2005 5:24 how to make my design as black box

hi brotherjam
but my issue is different. i wanna do full flow upto SI and RCx analysis . take all necessary data .
then i wanna take netllist after IPO (inplace opt) using cadence encounter.
finally i have to decide every thing OK........
then i wanna make this netlist to black-box.

ok i try this ur program in DC.
do u know equal command in RC(cadence)
let me know please
Thanks