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Dylan01
Joined: 06 Jul 2005 Posts: 17 Helped: 1
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23 Nov 2005 8:42 failed to open readmem file |
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I want to read a data file and take the data in memory,
while using following
$readmemb("data.dat", memory); (memory is a register array)
modelsim giving following error
** Warning: (vsim-7) Failed to open readmem file "data.dat" in read mode.
and it is not reading the correct data.
Why this error is coming and what is the solution.contents of data.dat are :
@000
00010010
00000011
@002
11111111 01010101
00000000 10101010
@006
1111zzzz 00001111
someone plz suggest solution
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echo47
Joined: 07 Apr 2002 Posts: 4206 Helped: 566
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23 Nov 2005 11:34 failed to open readmem file in read mode |
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No problem here. I created data.dat and then ran this is ModelSim SE 6.1b:
| Code: |
module test;
reg [7:0] memory [0:7];
integer n;
initial begin
$readmemb("data.dat", memory);
for (n=0; n<8; n=n+1)
$display("%b", memory[n]);
end
endmodule |
Results:
# 00010010
# 00000011
# 11111111
# 01010101
# 00000000
# 10101010
# 1111zzzz
# 00001111
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Dylan01
Joined: 06 Jul 2005 Posts: 17 Helped: 1
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23 Nov 2005 11:56 failed to open data file |
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this is the code . 1 thing here that code was working fine to me previously but now its not working . i wanted to know is there a problem in s/w shud i reinstall it ..
module readfile;
reg [7:0] memory[0:7];
integer i;
initial
begin
$readmemb("data.dat", memory);
for(i=0; i < 8; i = i + 1)
$display("Memory [%0d] = %b", i, memory[i]);
end
endmodule
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echo47
Joined: 07 Apr 2002 Posts: 4206 Helped: 566
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23 Nov 2005 12:55 failed to open readmem file in read mode. |
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Did the problem begin after you updated your ModelSim? Here are comments from various Release Notes:
Verilog Defects Repaired in 5.8e:
* A problem relating to $readmem resulted in memory leaks and large load times.
Verilog Defects Repaired in 6.0b:
* The system tasks $readmemh and $readmemb used to report an error when called with a memory that was either an automatic variable or a System Verilog class property
General Defects Repaired in 6.0e:
* $readmem for dynamic arrays did not work.
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Dylan01
Joined: 06 Jul 2005 Posts: 17 Helped: 1
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23 Nov 2005 13:39 modelsim readmemb |
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i dont know what was the problem but after reinstalling it started working fine..
anyway thnks for ur help
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23 Nov 2005 13:39 Ads |
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ohenri100
Joined: 15 Apr 2008 Posts: 1
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15 Apr 2008 18:36 modelsim file read and write |
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hi every body,
module test;
reg [7:0] memory [0:7];
initial begin
$readmemb("data.dat", memory);
end
endmodule
it not work, ...
please help me.
file data.dat :
@000
00010010
00000011
@002
11111111 01010101
00000000 10101010
@006
1111zzzz 00001111
Warning (10036): Verilog HDL or VHDL warning at test.v(2): object "memory" assigned a value but never read
Error (10054): Verilog HDL File I/O error at test.v(5): can't open Verilog Design File "data.hex"
Error: Can't elaborate top-level user hierarchy
Error: qu(at)rtus II Analysis & Synthesis was unsuccessful. 2 errors, 1 warning
Info: Allocated 134 megabytes of memory during processing
Error: Processing ended: Wed Apr 16 00:37:46 2008
Error: Elapsed time: 00:00:01
Error: qu(at)rtus II Full Compilation was unsuccessful. 2 errors, 1 warning
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