Clock divider by 3 with 50% duty cycle?

EDAboard.com Forum Index -> ASIC Design Methodologies & Tools (Digital) -> Clock divider by 3 with 50% duty cycle?

Author

Message

davyzhu

Joined: 23 May 2004
Posts: 521
Helped: 3
Location: oriental

17 Oct 2005 8:49 clock divider by 3

Hi all,

How to Build a Clock divider by 3 with 50% duty cycle?
Input and output are listed below.

Clkin
__--__--__--__--__--__--
Clkout
______------______------

Any suggestions will be appreciated!
Best regards,
Davy

Google
AdSense
Google Adsense

17 Oct 2005 8:49 Ads

Davood Amerion

Joined: 01 Mar 2005
Posts: 589
Helped: 90
Location: Persia

17 Oct 2005 8:59 divide by 3 clock

First you have to double input frequency, and then divide it by 3.
then divide it by 2 to produce 50% duty.
for doubling input frequency simply put one delay (such as RC, or buffer gates)
for example 20nS, then XOR input frequency and delayed one, you get 2x multiplayer.

Regards
Davood Amerion

Last edited by Davood Amerion on 17 Oct 2005 10:00; edited 2 times in total

IanP

Joined: 05 Oct 2004
Posts: 6490
Helped: 1542
Location: West Coast

17 Oct 2005 9:08 clock dividers made easy

Below is a circuit that divides incomming wave by 3 with 50% duty cycle ..
Reards,
IanP

Sorry, but you need login in to view this attachment

archillios

Joined: 29 Jun 2005
Posts: 97
Helped: 4

17 Oct 2005 9:45 clock divide by 3

I prefer Davood Amerion's method,
that would avoid clock glitching.

hi,IanP
can you assure there is no glitching in your combinational source of clock?

echo47

Joined: 07 Apr 2002
Posts: 4206
Helped: 566

17 Oct 2005 10:51 divider by 3

It looks glitch-free. It's from a Xilinx app note "Unusual Clock Dividers":
http://www.xilinx.com/xcell/xl33/xl33_30.pdf

The author repeatedly warns about possible simulator problems, but I have no problem simulating it in Verilog/ModelSim.

Both of these methods assume the input clock has 50% duty cycle, or else the output won't be symmetrical.

davyzhu

Joined: 23 May 2004
Posts: 521
Helped: 3
Location: oriental

17 Oct 2005 12:37 divide clock by 3

Hi Davood,

Thank you Smile

What's "and then divide it by 3." mean?
Is it 50% duty?

Any suggestions will be appreciated!
Best regards,
Davy

echo47

Joined: 07 Apr 2002
Posts: 4206
Helped: 566

17 Oct 2005 14:21 divide by 3 circuit with 50 duty cycle

The "divide it by 3" can be just an ordinary two-bit counter that goes 0,1,2,0,1,2,...

After doing those steps, you would have signals like this. For the output to have 50% duty cycle, the input clock must also have 50% duty cycle.

Sorry, but you need login in to view this attachment

anjali

Joined: 16 Aug 2005
Posts: 174
Helped: 8

17 Oct 2005 16:05 divide by 3 with 50 duty cycle

Davood Amerion wrote:

why dont we divide by 3 directly insted of multipliying by2, then divide by 3, and then divide by 2.

Davood Amerion

Joined: 01 Mar 2005
Posts: 589
Helped: 90
Location: Persia

17 Oct 2005 16:24 clock divided by 3

Dear davyzhu,
I think the echo47's answer is complete.

Dear anjali
Because when we directly divide by 3 we can't get 50% duty (insted we get 33.3% duty)

Regards

anjali

Joined: 16 Aug 2005
Posts: 174
Helped: 8

17 Oct 2005 17:37 clock divide 3

hai davood, we can get 50% duty cycle even by directly DIVIDE BY 3. by using 2 couters (one posedge triggered & one negedge triggered) & once total count equals 3, output clk need to be toggled. i followed int his way, instead of multiplying by 2, then divide by 3, then divide by 2.

davyzhu

Joined: 23 May 2004
Posts: 521
Helped: 3
Location: oriental

18 Oct 2005 1:42 divider 3

Hi echo47,

Why not go directly from "XOR" to "Divide by 6"?

Best regards,
Davy

archillios

Joined: 29 Jun 2005
Posts: 97
Helped: 4

18 Oct 2005 2:56 unusual clock dividers

oh, thanks to echo47 ,
your design is glitching free,the combinational based latch is great!

echo47

Joined: 07 Apr 2002
Posts: 4206
Helped: 566

18 Oct 2005 3:35 clock dividers

You guys are giving my too much credit. Wink

I drew the timing diagram to illustrate the suggestion by Davood Amerion.

The latch-based design was suggest by IanP. The design is from "Unusual Clock Dividers" by a Xilinx applications engineer.

davyzhu, an ordinary divide-by-6 counter that goes 0,1,2,3,4,5,0,1,2,3,4,5,... wouldn't have 50% duty cycle. By separating the counter into divide-by-3 and divide-by-2, you get 50%. (Actually, this still is a divide-by-6 counter, but with a funny count sequence.)

Someone asked me which program I used to draw that timing diagram. It's just lines drawn with a CAD program. I used good old OrCAD SDT for DOS. I still use it for large project schematics. I prefer it over all the modern tools.

nand_gates

Joined: 19 Jul 2004
Posts: 907
Helped: 120

18 Oct 2005 5:09 esnips + clock dividers made easy

Here is one more ckt in verilog!!

Code:

module clk_div3(clk,clk_out);
input clk;
output clk_out;

reg [1:0] cnt_p, cnt_n;
wire [1:0] cnt_p_nx, cnt_n_nx;

initial begin
cnt_p = 2'b11;
cnt_n = 2'b11;
end

assign clk_out = cnt_p[0] | cnt_n[0];
assign cnt_p_nx = {cnt_p[0],~(cnt_p[0] | cnt_p[1])};
assign cnt_n_nx = {cnt_n[0],~(cnt_n[0] | cnt_n[1])};

always @(posedge clk)
cnt_p <= cnt_p_nx;
always @(negedge clk)
cnt_n <= cnt_n_nx;

endmodule // clk_div3

You can add reset signal to remove the initial statement!

tut

Joined: 12 Dec 2003
Posts: 81
Helped: 5
Location: India

19 Oct 2005 16:38 2/3 divider 50% duty

CLOCK DIVIDERS MADE EASY
http://www.edaboard.com/download.php?id=30847

maxsnail

Joined: 29 Sep 2004
Posts: 93
Helped: 5

20 Oct 2005 2:02 verilog clock divider 50 duty cycle

Thanks. it is useful for me

nand_gates wrote:

Here is one more ckt in verilog!!

Code:

You can add reset signal to remove the initial statement!

tlihu

Joined: 02 Jan 2002
Posts: 669
Helped: 5

20 Oct 2005 3:43 clock divided by 3 circuit

Check this paper as well

http://www.edaboard.com/ftopic101951.html

Maybe it is the same as the one by tut.

blanket

Joined: 14 Jan 2003
Posts: 30
Helped: 1

30 Dec 2005 9:13 xilinx application note digital clock divider

If simplicity of design strikes you, then here's a solution.

If i have a 3 bit ring counter preloaded with a value 001, then I tap the output from any point, I'd have a divide-by-three 33% duty cycle output.

If i have another 3 bit-ring counter preloaded with same value 001, but clocked on the negative edge of the clock, I'd have another divide-by-three 33% duty cycle output with phase shift of 90 degree wrt the first output.

I OR these two outputs and I get a divide-by-three 50% duty cycle output. Am i right?

echo47

Joined: 07 Apr 2002
Posts: 4206
Helped: 566

31 Dec 2005 10:16 clock dividers made easy.pdf

Yes that would give a 50% duty cycle (assuming the input clock is square), however I wouldn't say a six-flop solution is "simplicity of design". Wink

By the way, if those two counters should ever fall out of sync (for example by a noise glitch or cosmic ray hit), then they would stay that way forever. I recommend using self-synchronizing logic wherever possible.

blanket

Joined: 14 Jan 2003
Posts: 30
Helped: 1

01 Jan 2006 17:27 clk divider 3

Just so that i understand the comment. Is Davood Amerion's solution the best available? Aren't there any issues in that circuit to produce 2x frequency square waves from a XOR gate and delay elements? Isn't designing the delay element more involved than putting six standard flops? I ask this so that i get the perspective...

echo47

Joined: 07 Apr 2002
Posts: 4206
Helped: 566

02 Jan 2006 12:58 clock division by 3

Lots of confusion here, because we are kicking around different ideas, and explaining each-other's messages. Wink

I don't like logic that relies on delays. I like the Xilinx application note that IanP suggested, however my favorite solution is a frequency multiplier based upon a DLL or PLL.

Last edited by echo47 on 02 Jan 2006 12:59; edited 1 time in total

blanket

Joined: 14 Jan 2003
Posts: 30
Helped: 1

02 Jan 2006 12:59 how to design a 50% duty cycle clock

Haha...Ok, I agree. Let's give this topic a rest! Very Happy

vipulsinha

Joined: 09 Nov 2005
Posts: 43
Helped: 3

20 Feb 2006 17:45 33 % duty cycle counter design

Hi
U can use 2 flop johnson counter for the div by 3 module. As johnson counter counts for 2N-1 cycle where N is the no of flops.

appleleaf

Joined: 27 Jun 2001
Posts: 18

21 Feb 2006 5:04 divide by 3 counter with 50% duty cycle

I think that using both edge of the input clock will be another soluation.

PitBull

Joined: 22 Jun 2004
Posts: 11

21 Feb 2006 14:47 50% duty cycle divide

I ve had this question before and there are a couple of replies on this site.
All credit to Satish B.

Sorry, but you need login in to view this attachment

littlefield

Joined: 07 Jul 2007
Posts: 25

14 Jul 2007 12:44 divide by three clock divider

hi
why should divide "XOR" by 3， then divide "divide3" by 2??????
WHY NOT divide "XOR" by 6 directly

when 0,1,2 ,the output is '0',
when 3,4,5 ,the output is '1',
it also have 50% duty cycle

echo47 wrote:

Last edited by littlefield on 17 Jul 2007 14:30; edited 2 times in total