electronics forum

Rules | Recent posts | topic RSS | Search | Register  | Log in

Hi need some info on Static timing analysis
Post new topic  Reply to topic    EDAboard.com Forum Index -> PLD, SPLD, GAL, CPLD, FPGA Design -> Hi need some info on Static timing analysis
Author Message
noorullam



Joined: 13 Oct 2005
Posts: 6
Post13 Oct 2005 7:29   

Hi need some info on Static timing analysis
Hi,
Can any one provide me some scenario's how to fix the setup and hold time violations. any material on static timing analysis
Back to top
Google
AdSense
Google Adsense
Post13 Oct 2005 7:29   

Ads


Back to top
omara007



Joined: 06 Jan 2003
Posts: 1283
Helped: 39
Location: Dubai
Post15 Nov 2005 10:25   

Re: Hi need some info on Static timing analysis
first .. u shoud not post such a question here .. but anyhow .. try to refer to the PrimeTime reference manual ..
Back to top
wadaye



Joined: 18 Jun 2004
Posts: 213
Helped: 10
Post16 Nov 2005 3:53   

Re: Hi need some info on Static timing analysis
Hi noorullam,

Basicly, you can reduce the combinational logic level, recuce the capacitance of the pin, and load of the pin to fix setup violation.

And you can add buf to fix the hold violation. But when you meet them both in the

same path, you have to resynthesize or rerouting.
Back to top
avimit



Joined: 16 Nov 2005
Posts: 417
Helped: 69
Location: Fleet, UK
Post17 Nov 2005 9:51   

Re: Hi need some info on Static timing analysis
Hi,
Fixing the setup and hold violation depends upon your design and the how to do it will depend upon the tools you are using. Hold violations are generaly fixed by inserting buffers in the path which is failing. Setup fix is not that straight forward. you may try to change the drive strengths of the cells in the path which is failing.
Kr,
Aviral Mittal
Back to top
alban



Joined: 05 Dec 2005
Posts: 10
Post06 Dec 2005 5:38   

Re: Hi need some info on Static timing analysis
hai,
inform for static timing analysis

Sorry, but you need login in to view this attachment
Back to top
Arabic versionBulgarian versionCatalan versionCzech versionDanish versionGerman versionGreek versionEnglish versionSpanish versionFinnish versionFrench versionHindi versionCroatian versionIndonesian versionItalian versionHebrew versionJapanese versionKorean versionLithuanian versionLatvian versionDutch versionNorwegian versionPolish versionPortuguese versionRomanian versionRussian versionSlovak versionSlovenian versionSerbian versionSwedish versionTagalog versionUkrainian versionVietnamese versionChinese version
Post new topic  Reply to topic    EDAboard.com Forum Index -> PLD, SPLD, GAL, CPLD, FPGA Design -> Hi need some info on Static timing analysis
Page 1 of 1 All times are GMT + 1 Hour
Similar topics:
need book or manual on Static Timing Analysis?? (4)
Static Timing Analysis-need good lab materials for Primetime (1)
How to define Static timing analysis and Dynamic Timing (3)
Static timing analysis and Dynamic timing verification (4)
Static Timing Analysis (22)
Static Timing Analysis (7)
Static timing analysis (3)
Static Timing Analysis (2)
Static Timing Analysis (52)
STATIC TIMING ANALYSIS (6)


Abuse || Administrator || Moderators || Support us || sitemap
topic RSS