Disable timing check in NC-Verilog

EDAboard.com Forum Index -> ASIC Design Methodologies & Tools (Digital) -> Disable timing check in NC-Verilog

Author

Message

ywguo

Joined: 09 Jan 2005
Posts: 18

10 Oct 2005 3:15 no_notifier

Hello,

I need to disable timing check for several instances on running post-layout simulation. The simulator is NC-Verilog.

Does anybody know how to disable timing check (setup time and hold time) for only several instances in NC-Verilog?

Thanks
Yawei

aji_vlsi

Joined: 10 Sep 2004
Posts: 640
Helped: 72
Location: Bangalore, India

10 Oct 2005 4:00 no timing check

Hi,
Perhaps you know this already: ncelab has a -notimingcheck - but that is a global switch - truns off for ALL instances.

If your concern is X-propagation due to timing violation (and not the violation iself), try using no_notifier flag, again global.

For instance specific stuff few ideas:

1. If you like this no_notifier kind of thing, it is fairly easy to create a TCL script to force notifier reg of each FF instance (that you are interested) to 0.
2. There is a PLI to do precisey what you wanted, see:
http://www.project-veripage.com/notc.php

3. IIRC, NC supports a system task named $disable_warning - to supress warnings from individual instances, search in their manual.

HTH
Ajeetha
--
www.noveldv.com
Interested in expert PSL/SVA training in Bangalore?
Visit www.noveldv.com/cvc.html

wls

Joined: 26 Jul 2001
Posts: 104
Location: Singapore

10 Oct 2005 5:55 ncverilog disable_warning

Hello aji_vlsi. If we disable the timing checks , is it going to make the post simulation less accurate ? Some eda simulation tools , rounded off negative timing checks for certain fab. Is it allowable , lets say for .35um ? Does it affect the accuracy of the timing info ?

How do we confirm or say , okay it can be neglect ? If STA tools like PT check alright but post simulation have message saying that no negative timing checks done. And the value os rounded to zero ? So is it valid , the post simulation if functional checks alright .

Thx in advance.

aji_vlsi

Joined: 10 Sep 2004
Posts: 640
Helped: 72
Location: Bangalore, India

10 Oct 2005 11:16 ncverilog no_notifier

Hi,

wls wrote:

Hello aji_vlsi. If we disable the timing checks , is it going to make the post simulation less accurate ?

Yes indeed, but that's where user intervens and says: i know this interface well, in real life these sginals don't toggle this way, hence let me ignore/turn them off.

Quote:

Some eda simulation tools , rounded off negative timing checks for certain fab. Is it allowable , lets say for .35um ? Does it affect the accuracy of the timing info ?

Many simulators do provide a way to enable -ve timing checks (-neg_thck ?)

I would prefer not to ignore -ve delays - unless you know what and why you are doing that.

Quote:

How do we confirm or say , okay it can be neglect ? If STA tools like PT check alright

Rely more on STA, do DTA (Dynamic, simulation) only for asynchronous stuff, sanity check and some functional tests.

Quote:

but post simulation have message saying that no negative timing checks done. And the value os rounded to zero ? So is it valid , the post simulation if functional checks alright .

Thx in advance.

As I mentioned, there are tool options to make these warnings disappear.

HTH
Ajeetha
--
www.noveldv.com
Interested in expert PSL/SVA training in Bangalore?
Visit www.noveldv.com/cvc.html

Google
AdSense
Google Adsense

10 Oct 2005 11:16 Ads

ywguo

Joined: 09 Jan 2005
Posts: 18

11 Oct 2005 8:02 negative timing check

Hi, Ajeetha,

Thanks very much. I really need to prevent the X state propagation.

I try the option -nonotifier for ncelab. Now it doesn't shown any timing violation and X state at the waveform.

Yawei