| Author |
Message |
wls
Joined: 26 Jul 2001
Posts: 104
Location: Singapore
|
 07 Oct 2005 0:54 Gate level debugging ??? |
|
|
|
|
Hello. Anyone one have good example between rtl/gate code and have tutorial/training on how to compare and debug between rtl/gate ?
Do we need to fix testbenches of rtl for gate level simulation even if the output function is correct and valid between rtl/gate simulation ?
If simulators like vcs at gate shows some setup/hold violation but the output of it and rtl function is correct , do we still need to fix testbenches ?
Anyone have example or tutorial , please help ?
Thx in advance.
Regards.
|
|
| Back to top |
|
 |
bronzefury
Joined: 04 Oct 2005
Posts: 39
Helped: 2
|
07 Oct 2005 16:35 Re: Gate level debugging ??? |
|
|
|
|
Sorry, I don't have a tutorial, but I can speak of this from experience.
If there is a setup/hold violation at gate level, my first approach would be to understand first why that is happening. For instance, it could be that the synthesis tool constraints are not correct or that the timing analysis constraints don't accurately model your chip. You'll need to understand if there is any discrepancy between what the synthesis tool reports and your gate level simulation. This task involves analyzing timing reports and comparing with gate level delays found in simulation.
I think from there, you'll have a good idea where the problem lies.
Altering any testbenches would be the last thing I would do.
|
|
| Back to top |
|
|
Google
AdSense
|
07 Oct 2005 16:35 Ads |
|
|
|
|
|
|
| Back to top |
|
|
anjali
Joined: 16 Aug 2005
Posts: 174
Helped: 8
|
08 Oct 2005 7:39 Re: Gate level debugging ??? |
|
|
|
|
hello bronzefury, i too have the same problem.
i did rtl simulation. i got the functionality.
then i did simulation. then i did synthesis & simulated the gate level netlist with the same thest bench.
i'm using NC-verilog.
simulator shows setup & hold violations. but the functionality is OK. i mean, the internal signals also ok. then if really any timing problems are there, how can i get the functionality. even internal signals are also generating properly at the expected clocks.
i'm not understanding. please explain me
Added after 1 minutes:
but timing reports are not showing any violations.
Added after 1 minutes:
but timing reports are not showing any violations.
|
|
| Back to top |
|
|
bronzefury
Joined: 04 Oct 2005
Posts: 39
Helped: 2
|
08 Oct 2005 13:23 Re: Gate level debugging ??? |
|
|
|
|
Hi Anjali,
Because your timing reports don't show any violations but simulations show setup/hold violations, you have a discrepancy. The timing report and simulator behavior should be the same. You'll need to figure out why they are different.
Maybe these steps might help..
1) On the simulator end, figure out which path to the D input of the destination flop is causing the setup/hold violation. Then write down the delay value starting from the clock input of the source flop to the D input of the destination flop. Also, note when the destination flop receives its clock source. What is important is to get a good understanding about how both flops receive their respective clocks and the signal propagation delay between the two flops. You want to be able to compare your findings here with your findings in a timing report.
2) Next, jot down how much time is violated on setup/hold. Is it a setup violation or a hold violation?
3) Once you've understood why it is failing in simulation, move to timing analysis.
4) Produce a timing report with the start path as the clock input of the source flop and the destination as the D input of the destination flop. You'll probably see combination logic and wire delays inbetween that contribute to propagation delay. Try and match up those delays with the delays you observe in the simulator. Write down which ones differ.
I think from there, you'll begin to have a clearer of view of why timing is failing.
|
|
| Back to top |
|
|
wls
Joined: 26 Jul 2001
Posts: 104
Location: Singapore
|
10 Oct 2005 5:47 Re: Gate level debugging ??? |
|
|
|
|
Hello bronzefury. Thx for ur reply . I always thought that dynamic simulation is for checking function and STA like Primetime checks timing ( whether it violates or not ).
So when doing gate simulation ( with backannotating sdf ) , how differ is it from STA tools result . The setup/hold violation is it valid if fuctional checks ok and STA okay ?
And to remove discrepancy , do we edit the testbenches to get clean gate simulation ?
Need more understanding on the role of setup/hold checks in gate simulation compare with STA tools ?
Thx in advance .
|
|
| Back to top |
|
|
bronzefury
Joined: 04 Oct 2005
Posts: 39
Helped: 2
|
10 Oct 2005 23:57 Re: Gate level debugging ??? |
|
|
|
|
Hi,
| Quote: |
So when doing gate simulation ( with backannotating sdf ) , how differ is it from STA tools result . The setup/hold violation is it valid if fuctional checks ok and STA okay ?
|
Well, you are going to have to analyze the results to know how the tools differ. Also, just because the functional portion runs fine and the STA is okay that you are in the clear. You'll need to figure out which tool is in error. They could be reporting false positives.
| Quote: |
And to remove discrepancy , do we edit the testbenches to get clean gate simulation ?
|
Find out why there is a failure first. It seems to me that you aren't sure yet. As if you are still at square one. Ask yourself, why does the simulator report a timing error but the others do not?
| Quote: |
Need more understanding on the role of setup/hold checks in gate simulation compare with STA tools ?
|
They play the same role.
|
|
| Back to top |
|
|
