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chihwt2003
Joined: 07 Jul 2005
Posts: 14
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 21 Sep 2005 13:03 JK flip-flop design |
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Hi,
Does anyone knows how to construct a JK flip-flop using Transmission gates or complex gate logic with a positive edge clock triggered?
Thanks in advance.
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nand_gates
Joined: 19 Jul 2004
Posts: 907
Helped: 120
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anjali
Joined: 16 Aug 2005
Posts: 174
Helped: 8
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21 Sep 2005 16:44 Re: JK flip-flop design |
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posedge triggered JK FF = -ve jk latch + +ve jk latch
latch can be designed using transmission gates easily.
for the latch design go through the book "CMOS fundamentals" (the title will be like that. i dont know the exact title, all most all people will follow that book)
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