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pseudockb
Joined: 04 Aug 2004
Posts: 89
Helped: 6
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 20 Sep 2005 2:08 site:www.edaboard.com cmos switch |
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| Hi, I would like to know how to determine the size of MOS switches. From what I know, the size should be small in order to have less charge injection but the size should be large to have a small "ON" resistance. Furthermore, I have frequently heard of people making use of half-size dummy switch to reduce charge injection. I would like to know why is it the dummy switch have to be half-size? Another thing that I am not sure of is whether the bulk connection of the NMOS switch should be connected to its source or to the ground. (N-well process) I find that both connection give a different voltage at its terminals. What is the common practice to tie the bulk connection and the reason behind it. Thanks in advance.
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flushrat
Joined: 25 Jan 2005
Posts: 191
Helped: 15
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20 Sep 2005 3:03 Re: Design of analog MOS switch |
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| The on-resistance requirement rather than charge injection determine the minum W. Half size dummu will absobe the injected charge from switch(assume half the charge flow to source and half to drain). Bulk connected to ground.
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20 Sep 2005 3:03 Ads |
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sunking
Joined: 25 May 2004
Posts: 914
Helped: 46
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20 Sep 2005 3:49 Design of analog MOS switch |
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avoid charge injection, you can use cmos switch and two phase clock, which Q1 Q2 and Q2', said Q2' is little more than Q2.
And you can referece some paper or book about adc
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pulkit shah
Joined: 24 Aug 2005
Posts: 11
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20 Sep 2005 13:02 Re: Design of analog MOS switch |
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| Dummy switch will have opposite polarity than the switch. You try to keep the falling edge of switch fast. Also dummy switch signal should have some delay compared to normal switch signal so that it can really cancell the charge.
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pseudockb
Joined: 04 Aug 2004
Posts: 89
Helped: 6
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22 Sep 2005 2:18 Re: Design of analog MOS switch |
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| Hi, I would like to clarify the statement of "Dummy switch will have opposite polarity than the switch". Do you mean that if the switch is NMOS, then the dummy should be a PMOS? Or do you mean that if the switch is on, then the dummy is off and vice versa? Thanks.
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arindrajiitkgp
Joined: 13 Jun 2005
Posts: 8
Helped: 2
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22 Sep 2005 14:04 Re: Design of analog MOS switch |
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hi
when you design a ckt then million of NMOS and PMOS are their. Now if all bulks are connected with gnd/vdd then vth of NMOS/PMOS does not change due to change of bulk voltage becaz all bulks are same potential. Now if you connected with source(when all sources are not connected with gnd) then vth changes due to change of bulk potential....it is effecting in your overall ckt.thanks
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nuiscet
Joined: 13 Sep 2005
Posts: 54
Helped: 3
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30 Sep 2005 6:43 Design of analog MOS switch |
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| How should we deal with the bulk voltage of the swtich MOSFETs?
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