why the logic untilization is different in 2 report?

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mhytr

Joined: 14 Dec 2004
Posts: 58

18 Sep 2005 15:03 why the logic untilization is different in 2 report?

Why the device utilization in synthesis report is different form the one in the place&route report?The first one seems reasonable ,the second one seems too small.The following are 2 reports of a same design.

untilization in synthesis report:
=========================================================================

Device utilization summary:
---------------------------

Selected Device : 3s400pq208-4

Number of Slices: 677 out of 3584 18%
Number of Slice Flip Flops: 562 out of 7168 7%
Number of 4 input LUTs: 1212 out of 7168 16%
Number of bonded IOBs: 48 out of 141 34%
Number of BRAMs: 6 out of 8 75%
Number of MULT18X18s: 4 out of 8 50%
Number of GCLKs: 1 out of 8 12%

=====================================================
untilization in place&route report:

Device utilization summary:

Number of External IOBs 49 out of 141 34%
Number of LOCed External IOBs 0 out of 49 0%

Number of RAMB16s 5 out of 16 31%
Number of SLICELs 261 out of 3584 7%
Number of SLICEMs 4 out of 1792 1%

Number of BUFGMUXs 1 out of 8 12%

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dynamicdude

Joined: 15 Mar 2005
Posts: 47
Helped: 1
Location: India

19 Sep 2005 9:29 Re: why the logic untilization is different in 2 report?

Actually the report after Place and Route will be specified normally by the minimum logic block of your FPGA. That is what has been done. But the IO numbers are all reported. When it comes to routing inside the FPGA, as you know it does block to block channel routing and Flops are all inside the CLBs itself. And so it does not report them at the end.

Wherein Synthesis can be done in a deviceindependent fashion which might report stil deep into the abstration upto the register levels.