verilog hdl or vhdl?

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bizoo

Joined: 22 Jun 2005
Posts: 93
Helped: 1

29 Jul 2005 18:43 verilog hdl or vhdl?

wat is the diffrence between the two wats better to learn ?

sawaak

Joined: 20 May 2003
Posts: 153
Helped: 4

29 Jul 2005 18:52 Re: verilog hdl or vhdl?

HI,
search the forum, as i remember, we have PLENTY of discussions regarding this topic Smile

also check the following
http://www.edaboard.com/ftopic98387.html

thanks
sawaak

z81203

Joined: 01 Aug 2001
Posts: 482
Helped: 3

31 Jul 2005 16:23 verilog hdl or vhdl?

ic or epld?
suggest verilog for ic.

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checkmate

Joined: 25 Feb 2004
Posts: 489
Helped: 35
Location: Toilet Seat

01 Aug 2005 0:52 Re: verilog hdl or vhdl?

I like verilog, except for those damn missing generate statements. Yes, I know Verilog2001 has them.
But the good thing about vhdl is type safety, makes them more easily scalable.

barkha

Joined: 08 Aug 2005
Posts: 114
Helped: 10
Location: India

16 Aug 2005 10:26 Re: verilog hdl or vhdl?

Verilog is easier to understand and use. For several years it has been the language of choice for industrial applications that required both simulation and synthesis. It lacks, however, constructs needed for system level specifications. VHDL is more complex, thus difficult to learn and use. However it offers a lot more flexibility of the coding styles and is suitable for handling very complex designs

Pls see the link for complete description
Verilog vs. VHDL: VHDL & Verilog Compared & Contrasted
Plus Modeled Example Written in VHDL, Verilog and C
h**p://www.angelfire.com/in/rajesh52/verilogvhdl.html

venkatesh_vlsi

Joined: 17 Aug 2005
Posts: 1

17 Aug 2005 13:32 Re: verilog hdl or vhdl?

verilog takes very less simulation time than the VHDL.
most of the companies uses only verilog HDL.
Verilog is easier for coding as it resemble C language.
Verilog syntax and semantics are very easier to understand
.

carrot

Joined: 23 Feb 2004
Posts: 173
Helped: 3
Location: Bangalore, India

20 Aug 2005 11:34 Re: verilog hdl or vhdl?

hi

Verilog is easy to start for hdl.
once u learn u can easily switch to vhdl.

rat_race

Joined: 01 Aug 2005
Posts: 124
Helped: 4

21 Aug 2005 12:13 Re: verilog hdl or vhdl?

i prefer verilog because its syntax is more similar to C++..!

aman

Joined: 25 Oct 2004
Posts: 145
Helped: 1

21 Aug 2005 21:37 Re: verilog hdl or vhdl?

go for verilog HDL any time if u have to choose b/w Verilog & VHDL
reason being verilog is much easier to learn , less complex and less time consuming
also if u r a beginner go for Palnitkar(for verilog Hdl)
u will find this book on betah.co.il (in Hardware subsection)
u may find it on EdaBoard but u have to search for it