electronics forum

Rules | Recent posts | topic RSS | Search | Register  | Log in

how to optimize a MUX with 256 input pins to reduce area?


Post new topic  Reply to topic    EDAboard.com Forum Index -> ASIC Design Methodologies & Tools (Digital) -> how to optimize a MUX with 256 input pins to reduce area?
Author Message
mark_alin



Joined: 26 Jul 2005
Posts: 2


Post26 Jul 2005 3:15   

how to optimize a MUX with 256 input pins to reduce area?


how to optimize a MUX with 256 input pins to reduce area? I find that the area of the MUX is too large.

thanks a lot!
Back to top
bg21359



Joined: 01 Mar 2005
Posts: 56
Helped: 2


Post26 Jul 2005 8:05   

Re: how to optimize a MUX with 256 input pins to reduce area


Maybe you can do 8:1 mux (total 32), then 8:1 mux(total 4), then 4:1 mux.
So total you need 36 8:1 mux and 1 4:1 mux
Back to top
Google
AdSense
Google Adsense




Post26 Jul 2005 8:05   

Ads




Back to top
papertiger



Joined: 28 Dec 2002
Posts: 66


Post28 Jul 2005 8:08   

Re: how to optimize a MUX with 256 input pins to reduce area


feed it into DC, I think the DC will give you a better result.
Mux may be to big for area, but it may be the least wire routing.
Back to top
soccer



Joined: 30 Jul 2004
Posts: 176
Helped: 2


Post28 Jul 2005 8:34   

how to optimize a MUX with 256 input pins to reduce area?


using dc to solve your problem. or other asic synthesis tools.
Back to top
amaccormack



Joined: 07 Jul 2005
Posts: 59
Helped: 3
Location: Scotland, UK


Post28 Jul 2005 10:21   

Re: how to optimize a MUX with 256 input pins to reduce area


If your synthesis tool cant improve the area much (make sure its optimizing for area, not time) then you may have other options, depending on what you are muxing. For example, making the outputs of the 256 things that you are muxing be =0 when not in use, then just ORing the outputs together. Or tristates, if your DFT methodology allows it (probably not a good idea). Or, can you rearrange these 256 things into a shift register structure. Or, if they are just memory elements, how about using a RAM instance?
Back to top
Arabic versionBulgarian versionCatalan versionCzech versionDanish versionGerman versionGreek versionEnglish versionSpanish versionFinnish versionFrench versionHindi versionCroatian versionIndonesian versionItalian versionHebrew versionJapanese versionKorean versionLithuanian versionLatvian versionDutch versionNorwegian versionPolish versionPortuguese versionRomanian versionRussian versionSlovak versionSlovenian versionSerbian versionSwedish versionTagalog versionUkrainian versionVietnamese versionChinese version
Post new topic  Reply to topic    EDAboard.com Forum Index -> ASIC Design Methodologies & Tools (Digital) -> how to optimize a MUX with 256 input pins to reduce area?
Page 1 of 1 All times are GMT + 1 Hour
Similar topics:
256 * 2 Mux 8??? (5)
how to reduce area? (9)
How to reduce the number of I/O Pins? (15)
HOW TO REDUCE AREA INSIDE THE FPGA (2)
how to reduce the input-offset of comparator (11)
CIC decimator circuit- How can I reduce the CIC filter area? (4)
How can to reduce offset in input terminal of OPamp ? (8)
how to optimize with ADS? (5)
reduce skew for clock pass through mux (11)
Using tri-state implementation to reduce area (4)


Abuse || Administrator || Moderators || Support us || sitemap
topic RSS