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chiara
Joined: 09 Jul 2002
Posts: 49
Helped: 3
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 10 Jul 2005 13:11 Multiple Vias in Power Line on PCB. |
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What do you think of multiple vias in power line to connect
TOP side to power plane?
There is a rule not to make loop on power line.
however the multiple vias breaks the rule in the literal sense.
Do you have any experience of measurement or
know the paper or resources dealing with this topic?
thanks in advance.
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bimbla
Joined: 13 Jul 2001
Posts: 541
Helped: 13
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10 Jul 2005 13:21 Re: Multiple Vias in Power Line on PCB. |
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In order to connect to the GND net using low impedance path, connection is made using multiple vias.
bimbla.
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jdhar
Joined: 16 Aug 2004
Posts: 261
Helped: 13
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10 Jul 2005 17:17 Multiple Vias in Power Line on PCB. |
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| The loop is relatively small, so I dont' think it's a problem as long as it's done near the source. If you are dealing with high currents, this is definitely needed.
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10 Jul 2005 17:17 Ads |
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pvskt
Joined: 25 Jun 2005
Posts: 44
Helped: 6
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12 Jul 2005 3:33 Re: Multiple Vias in Power Line on PCB. |
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| Loop areas formed are very negligible, so there is no question of EMI effects on the PCB.
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