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Adders in VHDL (Xilinx)
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osbourne



Joined: 13 Jun 2005
Posts: 48
Helped: 1
Post23 Jun 2005 14:44   

Adders in VHDL (Xilinx)
Hi,

is it better to use a simple "+" in VHDL coding to synthesize an adder or shall I use the available IP core for adders ? What is the difference ? It is more convenient to simply write "+" when adding several signal busses. When using the IP core component, I have to write more code lines. On the other side, the IP core may be optimized by Xilinx. Is this correct ?

Which one should I use ?

Regards,
Osbourne
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yego



Joined: 28 Oct 2004
Posts: 154
Helped: 14
Location: Middle of Nowhere
Post23 Jun 2005 14:58   

Re: Adders in VHDL (Xilinx)
I suggest that you should try to synthesize a simple circuit both ways and then you can compare the resource utilization and timings involved. The results will vary depending on the tool you are using, and sometimes on the coding style, so try several versions to pick the best one.

regards yego
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wolfheart_2001



Joined: 17 Mar 2005
Posts: 92
Helped: 9
Post23 Jun 2005 16:17   

Re: Adders in VHDL (Xilinx)
usually synthesis tools contain presynthesied blocks with optimal utilization of the
FPGA resources and adders is one of them, these cores give the optimal utilization only for FPGA's they were synthesized on, of course using the device specific cores is better but this reduce the portability of ur design to other FPGA architectures. xilinx for example fabricated FPGA's with build-in LUT which are designed to berform addition and multiplication operations quickly but other FPGA's dont contain LUT so the synthesized cores depend on the architecture used, so if u want only optimal utilization u can use these cores but if u to concentrate on the portability minimize their usage as possible.


good luck
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Sparc



Joined: 11 Apr 2005
Posts: 92
Helped: 14
Location: out of reach..
Post25 Jun 2005 10:55   

Re: Adders in VHDL (Xilinx)
It also depends on ur Input-width. No doubt using '+' is a more easy soln. and it also gives Synthesis tool to try all the available logic to fit best in the design. But, i have tried experimenting this and found that mostly XST implements Ripple Carry Adder. Latest FPGAs also have a Carry Forward logic in LUTs. What i think is if Adder is not your main constraint then let Tool handle '+', but if it's more frequent option and you don't care for H/W then you should go for available IP or ur dedicated with Fast logic. Again, it's more of pain but more efficient for your optimization Goal.
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shankar



Joined: 22 Jun 2005
Posts: 19
Helped: 2
Post25 Jun 2005 12:13   

Re: Adders in VHDL (Xilinx)
using "+" can implement any type of adders depending on algorithm. but if u need the system to operate in particular speed or area optimisation then u need to go for carrylookahead or carrysave adders (particularly in multipliers).



regards
shankar
mit
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Aser



Joined: 01 Jul 2004
Posts: 73
Helped: 5
Post25 Jun 2005 12:57   

Re: Adders in VHDL (Xilinx)
1) adder cores are usually relative placed macros,
therefore they provide maximum speed.
2) there are cores of adder-subtractor with +1,-1, etc. additional functions.
Such core is implemented with minimum hardware volume.
Similar ALU after synthesis usually affords much higher volume (depending on synthesator), or you have to use the specific template to get such ALU.

In anoher situations programming "+" is the best solution.
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