how can i detect the positive edge of a signal in verilog?

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superhet

Joined: 07 Jun 2005
Posts: 25

17 Jun 2005 3:23 find positive edge of signal

how can i detect the positive edge of a signal using an if statement in verilog. if i had to detect the level of a signal i would use

Code:

if(signal)
begin
........
........
end

but what if i want to detect only the positive edge of a signal???

my limited knowledge of verilog tells me that i could use

Code:

always @(posedge signal)
begin
..........
..........
end

but as i said im using an if statement which means im already in an always block and always blocks cannot be nested.

so what is the solution

dolby.yang

Joined: 02 Mar 2005
Posts: 74
Helped: 8

17 Jun 2005 3:53 detect edge signal verilog

u can use this circuit -------
-------------------------------------| | out signal
singnal - - -- - ------ | |----------------
------------ -------------- ----------|>。---------| |
- - --> - -> - not gate | ---|
clk ------ clk -------
DFF DFF

Added after 1 minutes:

u can use this circuit -------
-------------------------------------| | out signal
singnal - - -- - ------ | |----------------
------------ -------------- ----------|>。---------| |
- - --> - -> - not gate | ---|
clk ------ clk ------- and gate
DFF DFF

tom123

Joined: 04 Apr 2005
Posts: 116
Helped: 3

18 Jun 2005 8:52 positive edge signal

following code can detect a posedge :

wire signal_in;
wire edge_detected;
reg signal_d;

always @(posedge clk or negedge rst_n)
begin
if (~rst_n)
signal_d <= #1 1'b0;
else
signal_d <= #1 signal_in;
end

assign edge_detected = signal_in & (~signal_d);

best regards

superhet wrote:

how can i detect the positive edge of a signal using an if statement in verilog. if i had to detect the level of a signal i would use

Code:

if(signal)
begin
........
........
end

but what if i want to detect only the positive edge of a signal???

my limited knowledge of verilog tells me that i could use

Code:

always @(posedge signal)
begin
..........
..........
end

but as i said im using an if statement which means im already in an always block and always blocks cannot be nested.

so what is the solution

superhet

Joined: 07 Jun 2005
Posts: 25

18 Jun 2005 17:36 detect edge + verilog code

i forgot to tell you one thing. i want something that is synthesizable. the # operators are used in simulation and wont give me something that is synthesizable.