counter in vhdl

EDAboard.com Forum Index -> PLD, SPLD, GAL, CPLD, FPGA Design -> counter in vhdl

Author

Message

voho

Joined: 24 Feb 2004
Posts: 105

11 May 2005 15:24 counter in vhdl

Hi all,

how to do a counter 48 bits in vhdl because when i test my code i observed this problem:

hex:00 00 00 00 00 00
.....................
.....................
01 FF FF FF FF FF Surprised

k
01 00 00 00 00 00 :error
02 00 00 00 00 00 Surprised

k

it's a problem of carry i think?

Google
AdSense
Google Adsense

11 May 2005 15:24 Ads

cube007

Joined: 12 Mar 2002
Posts: 538
Helped: 12
Location: Australia

11 May 2005 15:50 counter in vhdl

It's something like this:

Code:

fpga_man

Joined: 27 Sep 2002
Posts: 18

11 May 2005 23:15 Re: counter in vhdl

cube007 wrote:

It's something like this:

Code:

signal cnt, cnt_nxt : std_logic_vector(47 downto 0);
begin
process (clk_i, reset_n_i) begin
if reset_n_i = '0' then
cnt <= 0;
elsif clk_i'event and clk_i = '1' then
cnt <= cnt_nxt;
end if;
end process;

cnt_nxt <= cnt + 1;

ok... you'd better write some GOOD vhdl!

first... put the numeric_std library on line.. => use ieee.numeric_std.all;

then the counter will be like this...

cpt_int is a signal 48 bits or what you want...;
cpt_out the output of the counter

process (raz, clk)
begin
if raz='1' then cpt_int<= (others => '0');
elsif rising_edge(clk)
then
if cpt_int= x"FFFFFFFFFFFF" then cpt_int<= (others =>'0'); --optional line (for simu!)
else cpt_int<=std_logic_vector(unsigned(cpt_int)+1);
end if;
end if;
end process;
cpt_out<=cpt_int;

that's all
good vhdl!

end beh;

nand_gates

Joined: 19 Jul 2004
Posts: 907
Helped: 120

12 May 2005 5:50 Re: counter in vhdl

Best way to design such a big counter is to divide it into smaller
counters. This will make counter hardware testing possble and easy!
Try to build 16 bit counter and instantiate it thrice to get 48 bit counter!