help--what's the different between vhdl and ahdl and verilog

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goodness

Joined: 24 Apr 2005
Posts: 0

25 Apr 2005 12:56 help--what's the different between vhdl and ahdl and verilog

hello！！　i am a colleage student from taiwan
i want to study hdl ,but i don't know what is the different between them
謝謝囉----thanks

Sparc

Joined: 11 Apr 2005
Posts: 92
Helped: 14
Location: out of reach..

25 Apr 2005 13:48 help--what's the different between vhdl and ahdl and verilog

The difference b/w these cannot be defined. The difference exists in the constructs used to code in these languages. All 3 are H/W description ;languages VHDL & VerilogHDL are standard HDLs, AHDL is a propreitary language of Altera.

Big Boy

Joined: 20 Jan 2004
Posts: 253
Helped: 10

25 Apr 2005 15:28 Re: help--what's the different between vhdl and ahdl and ver

VHDL and Verilog is as different as if you take the analogy between C++ and Delphi (PASCAL). Both have different syntax, but can achieve similar results.

People used to structured language might find it easier to start in Verilog. VHDL is more established than Verilog (and older). It is as, if as the first example above, 'C' compilers are older. They may not be the best option, but they are the industry standard. However, Verilog is gaining a lot of users, especially in the ASIC design field.

There are differences between VHDL and Verilog that are worth noting.

VHDL is higher level than Verilog. VHDL have, for example, libraries. You can put a whole block in a library, and then re-use it easily. With Verilog, you don't have that. Each time you wish to start a new project, and you take something usefull from another project, you have to take all the sources files individually. There is no notion of 'package'.

Verilog can go to lower level than VHDL. You can model at transistor-level (mos gates, ...). This is why it is often preffered for ASIC design.

Bottom line, VHDL is more supported than Verilog. You have more stuff on the Net available in VHDL. Companies ofted do VHDL tools before Verilog tools. Take for example the Xilinx EDK and the MicroBlaze soft processor, which are yet only generated in VHDL. Verilog is simpler to learn (IMHO), and is getting support rapidly.

Many of today's tools now support mixed-language synthesis. I.e. you can have a VHDL module instanced in a Verilog module or vice-versa.

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rprince006

Joined: 16 Jul 2004
Posts: 91
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25 Apr 2005 15:45 Re: help--what's the different between vhdl and ahdl and ver

Hi Big_Boy,

I agree with some of your points, but not all (sorry for that). ^_^

I think Verilog is getting more (and more) popular than VHDL, it is easy to learn
because it is quite samilar to another high-level language c/c++, so it is easier
to work with c/c++. Both Verilog and VHDL have their good sides and bad sides,
there are quite a lot articles talking about Verilog/VHDL and their difference.

I am quite not sure, but it is said some EDA vendors will not support VHDL anymore in your newest version. So many big companies are switching to
Verilog and SystemVerilg now.