how to design zero crossing comparator with single supply?

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ddt694

Joined: 12 Dec 2002
Posts: 175
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01 Apr 2005 17:33 how to design zero crossing comparator with single supply?

In a digital circuit board design, the high speed global clock may be from a TCXO or others. The output of the TCXO is sine wave sometimes. we must transform the sine wave to a square wave in order to clock some digital device, for example, FPGA or DSP.

We can use a zero crossing comparator to accomplish the process. With dual supply operation amp or comparator , the zero crossing comparator is very easy to design, but how to design it with a single supply system?

Can this circuit work well?

Thanks[img][/img]

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Last edited by ddt694 on 03 Apr 2005 16:11; edited 5 times in total

aryajur

Joined: 23 Oct 2004
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Location: Sunnyvale, USA

01 Apr 2005 20:28 Re: how to design zero crossing detector with single supply

Maybe we can use a capacitive level shifter and then see the zero crossing as a level crossing.

uk

Joined: 10 Feb 2005
Posts: 51

01 Apr 2005 21:29 Re: how to design zero crossing detector with single supply

Can you explain and give the circuit of the capacitive level shifter

MrEd

Joined: 26 Apr 2001
Posts: 104
Location: the Singularity

01 Apr 2005 22:10 Re: how to design zero crossing detector with single supply

I have noticed when making a zero cross detector for a dimmer, using the low voltage side of a transformer, that there will be a slight phase shift which you will need to compensate for in hardware or software. You must also filter out unwanted frequencies, making the phase shift even worse.

MrEd

aryajur

Joined: 23 Oct 2004
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Location: Sunnyvale, USA

02 Apr 2005 20:39 Re: how to design zero crossing comparator with single suppl

You could try a simple arrangement like the one shown in the figure.

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BigBoss

Joined: 17 Nov 2001
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02 Apr 2005 22:07 how to design zero crossing comparator with single supply?

If you connect -VEE to ground , you'll have a positive output comparator. Or use only a opamp with a high gain. This will also work.

pixel

Joined: 16 Sep 2004
Posts: 574
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03 Apr 2005 8:00 Re: how to design zero crossing comparator with single suppl

You can make comparator referred to dc level of sinusoid.. for example Vin-=Vdd/2.

dsjomo

Joined: 24 Oct 2003
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Location: Taiwan

04 Apr 2005 8:06 Re: how to design zero crossing comparator with single suppl

ddt694 wrote:

Maybe not. Because the noise might cause some unwanted glitches. Amplify the sine wave then use Schmitt trigger.

For example, if you are makeing a communication transceiver, and you are waveshping your clock signal for digital circuits, usually this clock is in MHz range. But this clock is easily affected by radio frequency local oscillator usually in GHz and hundreds MHz. Your clock signal now looks like a MHz sine wave carrying a GHz "ripple". If you don't use Schmitt trigger, instead you just simply compare the signal with a fixed DC, extra pulses occurs near zero crossing point.

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ddt694

Joined: 12 Dec 2002
Posts: 175
Helped: 5

04 Apr 2005 15:39 how to design zero crossing comparator with single supply?

Thanks to all friends.

To design a good comparator with single supply, I should:
1) set the right voltage bias point, for example, vcc/2, to avoid the noise trigger the comparator sometimes.
2) design comparator with hysteresis, like schmitt trigger to also avoid the affect of the noise.

Are these right?

Thanks

tecsiun

Joined: 20 Aug 2004
Posts: 9

04 Aug 2005 16:42 how to design zero crossing comparator with single supply?

the offset is important at the beginning of the comparison period. Due to the structure of a latched compartor (positive FeedBack), a small difference in its input should give an almost rail-to-rail output.

Fom

Joined: 10 Mar 2004
Posts: 778
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Location: Taiwan

05 Aug 2005 5:55 Re: how to design zero crossing comparator with single suppl

I have no graphic editor so I will only describe my idea.

2 NMOS (M1 and M2) current source connected to GND and to common gate bias.
Drains of these NMOS transistor are connected to 2 PMOS transistor configured as a current mirror, that connected to VCC.
Now disconnect the source of NMOS transistor that is connected NOT to PMOS diode. This disconnected source wil be input. The drain of this transistor is output.
It is just idea. You can add hysteresis and additional inverter to output to increse gain. And may be resistor divider to GND to reduce 1V amplitude of input signal to 0.3V or so.
Good luck!
Fom