how to implement reset circiut for pll

EDAboard.com Forum Index -> Analog Circuit Design -> how to implement reset circiut for pll

Author

Message

lovelonghair

Joined: 19 Mar 2005
Posts: 4

23 Mar 2005 14:28 how to implement reset circiut for pll

I want tot design a reset circuit for a pll,it is used to delay the power on,can somebody give me some advice or paper ,thanks very much

Vamsi Mocherla

Joined: 06 Sep 2004
Posts: 482
Helped: 62

24 Mar 2005 8:03 Re: how to implement reset circiut for pll

You can connect simple pull down transitors to each alternate stage of your VCO. The other stages can be pulled up(in case your stages are inverting). Then when RESET=1, all are pulled to ground.

Google
AdSense
Google Adsense

24 Mar 2005 8:03 Ads

jerryhuang

Joined: 03 Feb 2005
Posts: 39

24 Mar 2005 11:27 how to implement reset circiut for pll

what 's the name of this kind of circuit?

kjjian

Joined: 02 Dec 2005
Posts: 23

02 Dec 2005 16:01 how to implement reset circiut for pll

Power On Reset


	EDAboard.com Forum Index -> Analog Circuit Design -> how to implement reset circiut for pll

Page 1 of 1

All times are GMT + 1 Hour

Similar topics:
How to implement a PLL lock detector? (7)
how to replace F/F without RESET using F/F with RESET? (7)
protocol reset should be treat as syn reset or asyn reset? (5)
Altera PLL locked drives external reset? (1)
need circiut for pragram pic 16f84a (6)
How to add a software Reset for FPGA's (4)
how to implement DFT for DDR2 (3)
Working on a complicated circiut for fog lights using a mone (1)
How to do high fanout net setup for reset network in DC? (4)
How to quantize a number for DSP filter implement ? (2)

Abuse || Administrator || Moderators || Support us || sitemap

how to implement reset circiut for pll