verilog hdl

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akrlot

Joined: 14 Jan 2005
Posts: 57

08 Mar 2005 8:36 verilog hdl

hi;
why verilog is called as RTL langage?
could you give links/ebooks about verilog.Thx

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dolby.yang

Joined: 02 Mar 2005
Posts: 74
Helped: 8

08 Mar 2005 10:38 Re: verilog hdl

RTL:Register Transfer Level

http://www.verilog.com/

adap

Joined: 16 Feb 2005
Posts: 93
Helped: 11

08 Mar 2005 11:03 verilog hdl

When Verilog is used in RTL level then flip-flops (registers) are used. For this reason is called Register Transfer Level.
For ebooks have a look at the forum for Ebooks Upload/Download.

nemolee

Joined: 28 Dec 2004
Posts: 148
Helped: 2

08 Mar 2005 16:25 Re: verilog hdl

Not only verilog but also VHDL, if the code you write is based on Register Transfer Level, it is called RTL.

Wardong

Joined: 14 Feb 2005
Posts: 20
Helped: 2

08 Mar 2005 17:41 Re: verilog hdl

there are some books on verilog in the forum,u could search

always@smart

Joined: 08 Feb 2002
Posts: 308
Helped: 7
Location: ASIA

11 Mar 2005 10:52 Re: verilog hdl

adap wrote:

When Verilog is used in RTL level then flip-flops (registers) are used. For this reason is called Register Transfer Level.
For ebooks have a look at the forum for Ebooks Upload/Download.

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yes, what adap mentioned is what we also called "synthesizable verilog code". at RTL level, logic change depends on the clock for synchronize design. there is another level called behavirol level, in this level you just describe how ur design may function, it doesn't have to be in logic and register level, hence it's not synthesizable code.

hope i help u.

regards,
smart

baonguyenpro

Joined: 13 Oct 2006
Posts: 63
Helped: 2

11 Nov 2006 11:23 Re: verilog hdl

h**p://www.dientuftp.com/down/verilog

mingcol

Joined: 18 Aug 2006
Posts: 11
Helped: 1

12 Nov 2006 15:10 verilog hdl

verilog can be used for RTL description in front end design, besides, verilog can be for behavial description, extent to a good verifacation language via PLI, and many netlist can be in a verilog format.

vinod_g

Joined: 29 Nov 2006
Posts: 72
Helped: 6

01 Dec 2006 4:42 Re: verilog hdl

Any code that is synthesizable is called RTL. means register transfer where the created code synthesize to registers and the flow of data through that registers