Implement look up table in Verilog in FPGA using xilinx devi

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IamElectric

Joined: 03 Jan 2005
Posts: 10

07 Mar 2005 3:04 verilog lookup table

To implement a look up table for such as a multiplier, beside using a two dimentional array such as

reg [10:0] mem_arry[15:0]

and then initialize them in the "initial" block to the value you want?

Is there any other way of doing this?

I know that in VHDL, use can use two dimentional constant to implement a ROM look up table.

Besides using two dimentional array reg, and initialize in "initial" block, can someone recommend a different way?

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echo47

Joined: 07 Apr 2002
Posts: 4206
Helped: 566

07 Mar 2005 5:18 verilog lut

Which Verilog compiler are you using? Which Xilinx chip? Do you want to initialize block RAM or distributed RAM?

XST does not support the Verilog "initial" statement, so I have to use the agonizing "// synthesis attribute INIT_xx ..." syntax.

Even worse, ModelSim ignores those attributes, so I have to duplicate the whole thing using "defparam myrom.INIT_xx ..." syntax, and then surround that with "// synthesis translate_off" controls so XST won't explode. Aargh!

jarodz

Joined: 12 Mar 2005
Posts: 100
Helped: 14

12 Mar 2005 16:19 verilog look up table

My method to implement LUT-ROM is by using the matlab to print out the
the whole module in a single file like below:

module lut
(
in,
out,
);

input [7:0] in;
output [7:0] out;

reg [7:0] out;

always @(in)
begin
case(in)
0: out =
1: out =

endcase
end

endmodule

You can use other script language to do the same work.