Writing testbenches efficiently ... share your experience.

EDAboard.com Forum Index -> PLD, SPLD, GAL, CPLD, FPGA Design -> Writing testbenches efficiently ... share your experience.

Author

Message

afnam

Joined: 23 Dec 2003
Posts: 11

06 Feb 2005 11:47 Writing testbenches efficiently ... share your experience.

Hi all,

As for the process of design verification, I thought it would be useful if each one of us briefly demonstrates his/her own experience in building an efficient testbench to validate his/her design...

I only thought of the following items to be considered (of course you may want to consider others):

- Tools used to automatically generate testbench (if any).
- Testbench language used.
- Useful books (if any).
- % time allocated to verification phase (out of total design time).
- Comment and evaluate your experiment.
- What to consider next time.

Hopefully, this thread could become a reference for designers to continually learn about, evaluate, and compare different approaches for design validation.

Thanks for reading,
afnam.

semiconductorman

Joined: 18 Dec 2004
Posts: 153
Helped: 19

08 Feb 2005 4:59 Re: Writing testbenches efficiently ... share your experienc

Thought i could add a few more points here ...
# Methodology to be followed -> for example if your design has a processor in it u have the option of either using instruction driven testing ( h/w s/w co-simulation ) or using a bfm for your processor.
# System integration testing (u may choose to either simulate the whole system) or use c , C++ or system C to calculate bootleneck analysis etc
# Depending on how big ur desing is you may need to run a few application driven test cases