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crazyamd
Joined: 11 Jan 2005
Posts: 41
Helped: 2
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 05 Feb 2005 7:39 ADC simulation/characterization |
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is there a good simulation testbench for ADC simulation available? thanks!
Last edited by crazyamd on 10 Feb 2005 2:04; edited 1 time in total |
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steer
Joined: 14 Jan 2005
Posts: 122
Helped: 11
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| 09 Feb 2005 21:55 Re: ADC simulation/characterizationi |
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| Nothing at the simulation level. However you can take Teradyne, Shlumberger, Agilent test subroutines and convert them into Verilog-A.
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Vamsi Mocherla
Joined: 06 Sep 2004
Posts: 478
Helped: 61
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| 11 Feb 2005 16:58 Re: ADC simulation/characterization |
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| You can actually design a macro model of an ideal DAC to compare the inputs and the outputs. In some environments like Cadence, you can write Verilog A models
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crazyamd
Joined: 11 Jan 2005
Posts: 41
Helped: 2
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| 13 Feb 2005 8:05 Re: ADC simulation/characterization |
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| Vamsi Mocherla wrote: |
| You can actually design a macro model of an ideal DAC to compare the inputs and the outputs. In some environments like Cadence, you can write Verilog A models |
thanks for you guys' input. that's actually what i did. i'm just wondering if anyone has made a complete simu testbench/flow, preferrablly for cadence.
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