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Lord Loh.
Joined: 19 Jun 2004
Posts: 198
Location: Texas
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 29 Jan 2005 16:55 D Flip Flop with Preset and Clear... |
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I read in a book that the Clear and the Prest of a D Flip Flop are asynchronous inputs...
I doubt...The clear shall not propagate to the RS FF section unless the D is 0 and CLK high....and the PRESET shall not have effect unless CLK=1 and D=1....
So How really to use a D FlipFlop with Prest and Clear ?
And am I right to say that a the PRESET and Clear are a way to bypass the CLK and use the D Flip Flop as an RS Flip Flop ?
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checkmate
Joined: 25 Feb 2004
Posts: 489
Helped: 35
Location: Toilet Seat
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| 29 Jan 2005 17:19 Re: D Flip Flop with Preset and Clear... |
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The CLEAR/PRESET are asynchonous, ie they are independent of clock edges. In otherwards, they apply instantaneously and have precedence over clock transitions. Clocked operation will only occur when both are high.
This truth table pretty much summarises it.
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konqueror
Joined: 27 Nov 2004
Posts: 93
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| 29 Jan 2005 17:28 D Flip Flop with Preset and Clear... |
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| preset and clear are asynchronous inputs .whenever preset is 'active' irrespective of input and clock the output of flipflop becomes high.and in case of active clear input the output of flipflop becomes low irrespective of input and clock
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Lord Loh.
Joined: 19 Jun 2004
Posts: 198
Location: Texas
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| 05 Feb 2005 14:37 D Flip Flop with Preset and Clear... |
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If D and CLK are high, S=1 and R=0 (RS FF Section...) and now if I want to clear the FF the preset will not propagate to the flip flop...as they are and Gated...R=0 shall propagate only if CLk =1 and D=0
Am i wrong ?
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VVV
Joined: 26 Nov 2004
Posts: 1465
Helped: 269
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| 06 Feb 2005 3:47 Re: D Flip Flop with Preset and Clear... |
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I do not know which particular FF you are referring to, but if the datasheet says that the set andd reset inputs are asynchronous, that means they operate independently from the clock and data inputs. Once asserted, they will force the output in one of the possible states, even if there is a clock signal present and regardless of what the data input is. The effect is immediate.
Perhaps it would help if you posted the schematic you are referring to.
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Lord Loh.
Joined: 19 Jun 2004
Posts: 198
Location: Texas
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| 10 Feb 2005 19:38 Re: D Flip Flop with Preset and Clear... |
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The D flip Flop Diagramme...
So, will CLR work while D=1 ?
Will either PRE or CLR work if CLK=0 ?
Don't blame me if it is wrong.... I got it out of a book...
One solution I see is to replace the PRE and CLR AND gates with OR gates and keep the PRE and CLR active high...
Any comments ?
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marie65
Joined: 15 Jan 2002
Posts: 242
Helped: 10
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| 10 Feb 2005 20:12 Re: D Flip Flop with Preset and Clear... |
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Preset and Clear are asynchronous. The drawing from the book it's only for explanation purpose and it' s possible that the author didn't spot that's wrong. Here is the Texas Instruments implementation for D flip-flop
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shashi_reddy21
Joined: 09 Feb 2005
Posts: 28
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| 11 Feb 2005 7:59 Re: D Flip Flop with Preset and Clear... |
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| preset and clear in dare asynchronous as they do not depend on the d flipflop only the out put depends on the clk
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Lord Loh.
Joined: 19 Jun 2004
Posts: 198
Location: Texas
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| 11 Feb 2005 10:44 D Flip Flop with Preset and Clear... |
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Shouldn't it be called synchronous then if the output depended on the clock ?
I am begining to believe that the textbook had an error... It was a reputed book tough....
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MRFGUY
Joined: 16 Sep 2003
Posts: 109
Helped: 5
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| 15 Feb 2005 8:39 Re: D Flip Flop with Preset and Clear... |
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For synchronous case, the changes in output is depend on the clock. Even you give reset (preset) to low, output Q can't go to 0 (1) immediately, and have to wait until clock pos edge.
For asynchronous case, whenever clear(preset) is low, the output Q will be 0(1) immediately. No need to wait the clk pos edge.
(I just mention for the case of 74ls74 D flipflop, active low clear and preset, and pos edge clk)
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