VHDL: <= and := . What's the difference?

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yuenkit

Joined: 20 Jan 2005
Posts: 110
Helped: 5

27 Jan 2005 3:29 VHDL: <= and := . What's the difference?

Hi,

i am confused when I should use := and when I should use <= in VHDL.

Thank you.

eltonjohn

Joined: 22 Feb 2002
Posts: 1751
Helped: 28

27 Jan 2005 4:29 Re: VHDL: <= and := . What's the difference?

:= is used to initialize a variable :
MYVAR:='1' ;

<= is to used to initialise a signal ( a wire);
signal led_wire
led_wire <='1';

VHDL is a strongly typed language and some types use diffrent operators
But yes i think that they could have reduced the number of equivalent operators.

masai_mara

Joined: 13 Aug 2004
Posts: 118
Helped: 6

27 Jan 2005 4:54 Re: VHDL: <= and := . What's the difference?

Hi,
In vhdl the operator ":=" is used while initializing signals and variables when they are declared and the other instance being assignment to variables inside processes. The operator "<=" is used in assignment to signals inside a process and in continuous assingment outside a process.
hope its clear.

smith_kang

Joined: 22 Jan 2005
Posts: 90
Helped: 1

27 Jan 2005 5:55 Re: VHDL: <= and := . What's the difference?

you can thing in this way
:= it is used to realise blocking statements.so the statements with := are order dependent i.e. after executing first second will execute.but this is good in case of combinational circuit.othewise in sequential circuit it causes Race conditions.

<= is generally used to realise a non blocking statement.that is the statement with this sign are order independent.So if you are realising sequential circuit then better use <=.it will overcome race condition which will arise if you use :=

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crazy_man

Joined: 29 Dec 2004
Posts: 66
Helped: 2

27 Jan 2005 6:03 Re: VHDL: <= and := . What's the difference?

<= is used to assign values to an output port
:= is used to assign values for signal

the_penetrator

Joined: 22 Jun 2001
Posts: 327
Helped: 3

27 Jan 2005 14:22 Re: VHDL: <= and := . What's the difference?

crazy_man: what are you talking about? You don't know any VHDL, do you, just wanna get the points.

This topic has been already answered:

<= assign to a signal
:= assign to a variable

RH operands can be either signals or variables.

And to the one who started the topic: Please don't bother with VHDL. If you start asking for such elementary issues, do something else in your life.

Get it?

the_penetrator©