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shiningblue
Joined: 25 Jan 2005
Posts: 12
Location: USA
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 26 Jan 2005 16:37 verilog and VHDL |
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What is the difference between these two? which one is useful or popular?
verilog HDL means verilog or vhdl?
it might be a stupic question, but thanks for your answer.
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eltonjohn
Joined: 22 Feb 2002
Posts: 1558
Helped: 22
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| 26 Jan 2005 18:06 Re: verilog and VHDL |
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This is a very asked question .Several times we have debated about it .
No need to start over and over ..
Do some search at EDA all is here
HDL is both verilog and VHDL ..as well as others AHDL etc
Last edited by eltonjohn on 27 Jan 2005 3:06; edited 1 time in total |
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eltonjohn
Joined: 22 Feb 2002
Posts: 1558
Helped: 22
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| 27 Jan 2005 3:12 Re: verilog and VHDL |
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VHDL = VHSIC hardware description LANGUAGE
VHSIC = Very High Speed Integrated Circuit
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Prashant Mishra
Joined: 28 Jan 2005
Posts: 3
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| 02 Feb 2005 6:42 Re: verilog and VHDL |
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both are hardware description langauge.veriolg is similar to C langauge and VHDL is like ADA.
verilog HDL means verilog langauage.
both are popular and useful.
Added after 1 minutes:
both are hardware description langauge.veriolg is similar to C langauge and VHDL is like ADA.
verilog HDL means verilog langauage.
both are popular and useful.
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crazy_man
Joined: 29 Dec 2004
Posts: 66
Helped: 2
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| 02 Feb 2005 8:29 Re: verilog and VHDL |
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both are used for designing logic..
Invariably the selection of the language depends on the vendor..
Not much difference between the two...
VHDL is more elaborative than verilog. I have felt that VHDL is a lot more easy to understand than verilog.. But seriously, there is no much difference between the two..
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smith_kang
Joined: 22 Jan 2005
Posts: 90
Helped: 1
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| 02 Feb 2005 10:46 Re: verilog and VHDL |
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hi
verilog and VHDL are both Hardware Description Langauages.
Verilog and VHDL both are now industry standard for writing code for Hardware.
Verilog is very much close to C langauge and VHDL is close to PASCAL.One thing you must remember VHDL is very strongly typed langauge and you must follow the rules accordingly.
Verilog is simple to learn.You can start with this langauge.
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j2005
Joined: 17 Jan 2005
Posts: 44
Helped: 5
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| 03 Feb 2005 4:19 Re: verilog and VHDL |
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| I have coded with both before and seriously, I don't see much difference other than the syntax. You know one, and you'll pick up the other easily. At the end of the day, just learn whatever your school/ work uses.
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arp
Joined: 27 Jan 2005
Posts: 50
Helped: 5
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| 03 Feb 2005 6:05 Re: verilog and VHDL |
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if u r good in C then u feel verilog is easier one otherwise VHDL is easy.
in my view for learners VHDL is easier one but when u go for big designs u feel uncomfortable by using this unless u know syntaxes correctly
anyway i feel VHDL is easier than verilog.
whats ur views
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laocai
Joined: 30 Dec 2003
Posts: 19
Location: china
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| 06 Feb 2005 12:53 Re: verilog and VHDL |
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| i think verilog is easy to use
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mipedja
Joined: 20 Sep 2004
Posts: 28
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| 06 Feb 2005 16:07 Re: verilog and VHDL |
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VHDL is familiar with ADA
Verilog is familiar with C
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shashi_reddy21
Joined: 09 Feb 2005
Posts: 28
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| 11 Feb 2005 8:03 Re: verilog and VHDL |
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| VERILOG and VHDL both are used for coding ,but recnetly i found that most industries use VERILOG only.
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ikru26
Joined: 01 Feb 2005
Posts: 112
Location: INDIA
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| 11 Feb 2005 8:24 Re: verilog and VHDL |
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Both VHDL and Verilog are Hardware discription languages and compatable with simulation and synthesis tools. There are some abstraction levels of any digital design as system level(top level OF abstraction ), then module level, gatelevel, circuit level, device level.
In VHDL we can write the program upto gate level only and also we can see the hardware upto gate level only but in Verilog we can write the code and see the harware upto circuit level. this is the main difference between them. there are some more differences , i will tell you if you are more interested.
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subdural
Joined: 21 Aug 2004
Posts: 78
Helped: 3
Location: Neutral Zone
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| 11 Feb 2005 10:19 Re: verilog and VHDL |
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| Since both VHDL and Verilog is HDL, is that possible to interfacing or convert both language to be understand each other? Any tools can do this?
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omid219
Joined: 02 Feb 2005
Posts: 120
Helped: 4
Location: Malaysia
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| 15 Feb 2005 9:55 verilog and VHDL |
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there are some tools for C to VHDL/Verilog conversion, but have not seen such a this software for VHDL 2 Verilog conversion.
BTW, I myself have worked with both VHDL & Verilog, I think coding time in verilog is less than vhdl.
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bloodemon
Joined: 17 Feb 2005
Posts: 22
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| 17 Feb 2005 1:13 Re: verilog and VHDL |
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I think both of the languages are useful, once you know one well, you can pick up the other one easily. However, they do have some difference, here is a good comparison article, maybe you can take a look.
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