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Strange PLL lock problem?

 
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cqmyg5



Joined: 21 Oct 2003
Posts: 137
Helped: 1


Post08 Jan 2005 2:44   Strange PLL lock problem?

Hello,

I am testing a 2.4G PLL.
This PLL couldn't lock if just after power-on, and vco free-run at 2480MHz, vtune=0v. When I increse both vco current and vco's tuning cap, the PLL can now lock in 2400M-2490MHz. After this, I decrese both vco current and vco's tuning cap to original value, then the PLL also can lock 2400M-2490MHz.

Why the PLL could lock after it has been increased and then decreased current and cap, since the value is as same as it's just after power-on?

Thanks!
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Analog_starter



Joined: 15 Nov 2004
Posts: 118


Post18 Jan 2005 15:15   Re: Strange PLL lock problem?

For a PLL circuit, you must check its loop characteristics.
Matlab is a good choice.
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purefen



Joined: 20 Jun 2004
Posts: 16


Post19 Jan 2005 5:20   Re: Strange PLL lock problem?

Dear:
The pfd output should be checked first. IF the pfd work correctly, the vtune should be raise. Because u say that ur vtune is always zero after power on.
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