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borodenkov
Joined: 02 Mar 2004
Posts: 129
Helped: 11
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 06 Jan 2005 3:39 ahdl and veriloga |
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In the ahdlLib in Cadence there are "ahdl" and "veriloga" views. The synthax is different.
I am confused with the difference between them. "veriloga" should be a Verilog-A model. It seems that "ahdl" stands for SpectreHDL language - what is it?
Which model is better to use?
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field_catcher
Joined: 27 Dec 2004
Posts: 26
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| 06 Jan 2005 4:22 Re: ahdl and veriloga |
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| As far as I know, ahdl is phasing out. Verilog-A is the one to use. Verilog-A is the analog subset of emerging language Verilog-AMS.
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geconom
Joined: 12 Feb 2002
Posts: 295
Helped: 3
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| 06 Jan 2005 16:07 Re: ahdl and veriloga |
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| Also, ahdl may be replaced by VHDL-AMS.
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borodenkov
Joined: 02 Mar 2004
Posts: 129
Helped: 11
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| 07 Jan 2005 2:00 Re: ahdl and veriloga |
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| geconom wrote: |
| Also, ahdl may be replaced by VHDL-AMS. |
I do not think they are similar. I looked more careful at Cadence docs, "ahdl" is SpectreHDL, Cadence analog simulation language with syntax very close to Verilog-A.
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cube007
Joined: 12 Mar 2002
Posts: 538
Helped: 12
Location: Australia
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| 07 Jan 2005 9:06 ahdl and veriloga |
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| I know AHDL only as @ltera HDL for digital designs. The nomenclature is a little bit confusing.
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