How to design a high performance mos switch?

EDAboard.com Forum Index -> Analog IC Design & Layout -> How to design a high performance mos switch?

Author

Message

yyliang

Joined: 26 Aug 2004
Posts: 44

23 Dec 2004 5:52 How to design a high performance mos switch?

Hello, I am designing a switched capacitor integrator,but I encountered a difficulty in design the switches, it seems that there is current leakage from the source or drain,can someone help me?How can I get a high performance mos switch?
Thanks in advance.

IanP

Joined: 05 Oct 2004
Posts: 6490
Helped: 1542
Location: West Coast

23 Dec 2004 6:21 Re: How to design a high performance mos switch?

Is there any reason why you can not use integrated switch CD4066?
Inside you will find 4 bilateral switches.

sunking

Joined: 25 May 2004
Posts: 914
Helped: 46

23 Dec 2004 6:27 Re: How to design a high performance mos switch?

it is diffcult to do.
contact the foundry, require them well control.

And you can add the switch "L", make sure not the smallest .

xuel

Joined: 16 Nov 2004
Posts: 397
Helped: 11

23 Dec 2004 7:28 Re: How to design a high performance mos switch?

first the ratio of W/L should be optimized, then choose a suitalbe absolute value of W and L. If still couldn't satisfy requirement, use dummy device or adopt bootstraping or bottom-plate sampling technique.

andy2000a

Joined: 18 Jul 2001
Posts: 767
Helped: 7

23 Dec 2004 8:07 Re: How to design a high performance mos switch?

mos switch for Sample/hold need low leakage , simple mos like CD4016
is better than CD4066 ,

but cmos switch CD4066 have low Rds ..

In asic design , you cn use "dummy sw" reduce charge_inject & clock feed_thru
maybe "unless" --> some porfessor said even text book said
add dummy switch can reduce charge_inject

another problem is mos Rds & Vth drop on mos switch
in some volt double circuit like charge pump use pmos for Hi-v input
(nmos vo= vin -vtn) but even though .. vin = 2* vin -v1 ..

I simulation find Vo= 6.16v not 3.3v*2=6.6 still have volt drop
cmos switch I use 20/0.5 * 200 size ..

have anyone ever design charge_pump ASIC , Io=100ma
can you tell me how to design mos switch

eda4you

Joined: 17 Sep 2002
Posts: 283
Helped: 17

11 Jan 2005 15:25 Re: How to design a high performance mos switch?

The use of differential circuits will help decreasing charge injection. Look at basic lieterature like that CMOS DESIGN (Razzavi).

yyliang

Joined: 26 Aug 2004
Posts: 44

12 Jan 2005 6:22 Re: How to design a high performance mos switch?

Should the clock of PMOS and NMOS be definitely opposite phase?

andy2000a

Joined: 18 Jul 2001
Posts: 767
Helped: 7

12 Jan 2005 8:35 Re: How to design a high performance mos switch?

I "guess" eda4foru means , some use switch circuit like
flash A/D convert use switch cap + preamp cirucit usually use
differential signal path ..

but I problem is use mos switch for , charge_pump circuit ..
pump 1.5v -> 5.5v output , and use good switch reduce volt_drop & Rds on ..

Google
AdSense
Google Adsense

12 Jan 2005 8:35 Ads

konqueror

Joined: 27 Nov 2004
Posts: 96

15 Jan 2005 10:37 How to design a high performance mos switch?

u can use a dummy switch or a transmission gate switch to minimize the leakage from source and drain.also for the switch u require the on resistance to be very low so optimize the w/l ratio.clock for dummy switch is somewhat delayed w.r.t. switch

dumbfrog

Joined: 17 Jul 2004
Posts: 192
Helped: 4

18 Jan 2005 2:41 Re: How to design a high performance mos switch?

increase the L and optimize the W

zhangjun_qh

Joined: 20 Feb 2003
Posts: 1
Location: China

19 Jan 2005 7:19 How to design a high performance mos switch?

For the analog ic design, you just need to select right topology, then base on the what's clock frequency and signal frequency is, work out a reasonable settling time, to decide the switch W and L, then use a bootstrapping clock for critical switch. Please forget dummy switch, it is not true at some case.

mitrobge

Joined: 19 Feb 2005
Posts: 49
Helped: 3
Location: GREECE

16 Mar 2005 23:48 Re: How to design a high performance mos switch?

can you give some information about efficiency of clock bootstrapping for (pass-gate) switch and bulk-source forward-biased polarization at 0.12u technology?