electronics forum

Rules | Recent posts | topic RSS | Search | Register  | Log in

AHDL syntax clarification


Post new topic  Reply to topic    EDAboard.com Forum Index -> ASIC Design Methodologies & Tools (Digital) -> AHDL syntax clarification
Author Message
mohd_ind00



Joined: 17 Dec 2004
Posts: 26


Post17 Dec 2004 15:25   

ahdl syntax


Hi all...

Pl see the below code and explain, how it evalvates a constant with bus in AHDL..

var1[9..0] = var2[9..0]+12;

And is the following syntax valid for bus decleration..(want only these lines in bus)

add_bus[15,14,10..0]

reply if any knows.

regards!
Back to top
Google
AdSense
Google Adsense




Post17 Dec 2004 15:25   

Ads




Back to top
shashavali



Joined: 18 Dec 2004
Posts: 3


Post18 Dec 2004 11:55   

ahdl bus syntax


hi,

i think second one is not possible..
Back to top
Arabic versionBulgarian versionCatalan versionCzech versionDanish versionGerman versionGreek versionEnglish versionSpanish versionFinnish versionFrench versionHindi versionCroatian versionIndonesian versionItalian versionHebrew versionJapanese versionKorean versionLithuanian versionLatvian versionDutch versionNorwegian versionPolish versionPortuguese versionRomanian versionRussian versionSlovak versionSlovenian versionSerbian versionSwedish versionTagalog versionUkrainian versionVietnamese versionChinese version
Post new topic  Reply to topic    EDAboard.com Forum Index -> ASIC Design Methodologies & Tools (Digital) -> AHDL syntax clarification
Page 1 of 1 All times are GMT + 1 Hour
Similar topics:
AHDL Book (1)
FFT in AHDL (1)
About AHDL (2)
AHDL language help !!!!! (4)
ahdl and veriloga (4)
AHDL and VHDL (3)
Cadence Ahdl Op Amp (4)
where is ahdl to vhdl converter? (2)
convert AHDL, ABEL to VHDL (5)
Design FIR Filter In AHDL (2)


Abuse || Administrator || Moderators || Support us || sitemap
topic RSS