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Analog_starter
Joined: 15 Nov 2004
Posts: 117
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 13 Dec 2004 2:04 About VCO gain |
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Hi all,
The VCO gain varies hugely under different corners, such as tt, ss, ff, low temp, high temp, low power, and high power. What is the practical value that I can put it into the system level simulation?
If I want to design a VCO with 500M~1G tuning range, 1.8V power supply. What is the best VCO gain? It can reach the 1G frequency under the tt, room temp, 1.8V, but failed in ss,low temp,and low vdd. While meet the output under the worst case, The VCO gain is so huge in normal or fast corner (about > 1.5G/V). How can I solve this conflict?
Does the bigger VCO gain mean the bigger output jitter?
I am really puzzled with them.
Thanks & Best Regards
Analog_starter
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huanchou
Joined: 23 Aug 2004
Posts: 44
Helped: 2
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| 13 Dec 2004 8:50 Re: About VCO gain |
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The VCO gain is decided by your low pass filter voltage range.
What kind of CAP do you use?
I think maybe you can try to use the SS corner to design the VCO first then extend
to other corners.
The larger VCO gain is, the worse jitter performance has.
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simonkuo
Joined: 02 Nov 2004
Posts: 29
Helped: 2
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| 13 Dec 2004 10:34 Re: About VCO gain |
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In my experience, It will have at least 3 times difference in FF and ss corners ( include the bias, cap...corners).
What is your VCO construction?
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Analog_starter
Joined: 15 Nov 2004
Posts: 117
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| 13 Dec 2004 14:09 Re: About VCO gain |
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Hi huanchou,
I use MOS CAP in order to reduce die size.
But when it meets the output under the SS corner , The VCO gain is very huge in tt or ff corner. What is the practical VCO gain value that I can put it into the system level simulation?
Hi simonkuo,
It is just a three-stages ring oscillator. And how do you deal with the 3 times difference?
Thanks & Best Regards
Analog_starter
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huanchou
Joined: 23 Aug 2004
Posts: 44
Helped: 2
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| 14 Dec 2004 5:52 Re: About VCO gain |
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The practice VCO gain is decided by your selected foundry.
Some foundries usually tune their process to TT or FF corner but some not.
But due to the chips need to be packaged, the VCO gain are usually smaller than your simulation results.
So you should analyze your WAT data, to check which coener they deviate to.
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simonkuo
Joined: 02 Nov 2004
Posts: 29
Helped: 2
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| 14 Dec 2004 6:03 Re: About VCO gain |
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If I select the foundry of TSMC, I will check the TT and FF corners.
If I select the foundry of hynix, I will check the SS and TT corners.
If I select the foundry of UMC, I will check the SS and TT corners.
for your reference.
BR.
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Analog_starter
Joined: 15 Nov 2004
Posts: 117
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| 14 Dec 2004 6:21 Re: About VCO gain |
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Does it mean nobody can always promise that his(or her) VCO can work at every process corner, especially for high frequency output?
Thanks & Best Regards
Analog_starter
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simonkuo
Joined: 02 Nov 2004
Posts: 29
Helped: 2
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| 14 Dec 2004 6:53 Re: About VCO gain |
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It will take the tract-off between your circuit margin and your performance.
If you want to design the larger circuit margin, you will lose the more circuit peformance.
If you want to fit all of the process corners, you have to design the large VCO gain, but its jitter performance will worse.
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Analog_starter
Joined: 15 Nov 2004
Posts: 117
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| 14 Dec 2004 8:40 Re: About VCO gain |
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Thank you all!
Thanks & Best Regards
Analog_starter
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