arunragavan
Joined: 01 Jul 2004
Posts: 487
Helped: 21
Location: India
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 12 Dec 2004 21:47 Re: output stage bias |
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take a look at the open loop buffer schematic..( attachment)
that explains when the output stage is biased..
hope this helps
with regards,
/Files deleted. Post links instead of files.
http://www.ece.ucsb.edu/Faculty/rodwell/Classes/ECE137A/amplifier_gallery.pdf
http://pdfserv.maxim-ic.com/en/an/AN378.pdf
(klug)/
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