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nxing
Joined: 10 May 2004
Posts: 446
Helped: 12
Location: China
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 08 Dec 2004 14:20 constant_gm circuit |
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Hello everyone,
I have a question regarding the Constant_Gm circuit, refering to the attched picture or Razavi's book at page 381. I just wondering whether or not we can change the branch of the diode connected transistor(like the right picture). Is it still a constant_gm circuit under that connection?
Thanks
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yeewong_su
Joined: 12 Oct 2004
Posts: 126
Helped: 3
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| 09 Dec 2004 2:48 constant_gm circuit |
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| I think you can find the reason by using the small signal model.
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gevy
Joined: 17 Nov 2004
Posts: 377
Helped: 41
Location: Russia
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| 09 Dec 2004 17:45 Re: constant_gm circuit |
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I think the right circuit is bad and it will not work because of instability.
Try to simulate it.
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sutapanaki
Joined: 02 Nov 2001
Posts: 488
Helped: 19
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| 09 Dec 2004 20:17 Re: constant_gm circuit |
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I think you don't have to do a small signal analysis to understand why the circuit on the right is not correct. There are two types of feedback in these so called self-biased circuits - positive and negative. The positive one is responsible for making the current increase, while the negative is responsible for stoping the increase of that current. When both feedback loops are happy, the circuit finds its stable point. Usually, as you know there are two such stable points, that's why you need a start-up circuit.
For the circuit on the left the positive feedback loop includes the NMOS transistors and the PMOS transistors. I think this is not difficult to see. The negative feedback loop includes the gate-source voltage drops of the two NMOS transistors and the resistor. The thing is that the Vgs of the diode connected NMOS transistor tends to saturate with increasing the current, because it is changing by a square-root law - well, to a certain extend. So the gate of the NMOS transistor with the resistor in its source changes slower than its source voltage, which is defined by a linear change because of the resistor. When you take the usually 1:1 PMOS mirror into account you'll see that ultimately the circuit settles at a certain value of the current.
For the circuit on the right, the positive feedback is still there, but there is no negative feedback any more. If the current in the diode connected NMOS transistor and the resistor increases for some reason, this will bring an increase in the gate voltages of the NMOS transistors. Here the resistor doesn't limit the current increase. So, the gate voltages increase, the current in the not-diode connected transistor also increases. Then that current gets mirrored back to the right branch which will increase its current again and so on. Most probably the circuit will saturate.
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