1. Announcement:
    Forum rules & policies (quick reference)
    alexan_e (Administrator)
    7th August 2014
    Views:
    96,341
Page 1 of 616 1 2 3 11 51 101 501 ... LastLast
Threads 1 to 30 of 18471

Forum: Analog Integrated Circuit (IC) Design, Layout and Fabrication

Analog Integrated Circuit Design, Layout & Fabrication Questions. Analog ASIC Design. Semiconductor Technology Issues.

  1. Sticky Thread Sticky: Featured Reference Designs

    Started by mmatheson, 16th June 2016 22:04
    • Replies: 0
    • Views: 5,868
    16th June 2016, 22:04 Go to last post
  2. Sticky Thread Sticky: Read this before posting

    Started by klug, 3rd December 2007 18:00
    • Replies: 0
    • Views: 25,003
    3rd December 2007, 18:00 Go to last post
  1. Determine Technology Current using foundry models

    Started by deveshkm, 9th August 2017 08:03
    2 Pages
    1 2
    • Replies: 33
    • Views: 2,682
    Today, 15:44 Go to last post
  2. Technology nodes and Circuit design variation

    Started by kaushikrvs, 14th October 2017 08:22
    • Replies: 1
    • Views: 344
    14th October 2017, 18:15 Go to last post
  3. Calibre xRC Extraction Device Overlap

    Started by ljp2706, 5th October 2017 13:26
    • Replies: 11
    • Views: 720
    13th October 2017, 13:58 Go to last post
  4. Moved: RE: differential loss cadence

    Started by kenambo, 12th October 2017 11:58
    •  
    •  
  5. Moved: DC DC Converter parameters

    Started by gkkrish52, 12th October 2017 08:48
    •  
    •  
  6. Moved: Is it possible to create our own IC in Pspice software?

    Started by letlive, 11th October 2017 18:01
    •  
    •  
    • Replies: 11
    • Views: 1,098
    10th October 2017, 11:53 Go to last post
  7. Moved: Comparator Desing paper

    Started by Ali_sh, 9th October 2017 19:38
    •  
    •  
  8. diode model for Cadence

    Started by bio_man, 8th October 2017 03:38
    • Replies: 13
    • Views: 681
    9th October 2017, 19:05 Go to last post
  9. Optimizer in Cadence ADE-GXL

    Started by pancho_hideboo, 9th October 2017 11:44
    • Replies: 0
    • Views: 213
    9th October 2017, 11:44 Go to last post
  10. Latchup prevention using Deep Nwell

    Started by Jarvsiri, 7th October 2017 19:07
    • Replies: 1
    • Views: 292
    8th October 2017, 17:19 Go to last post
  11. Moved: standard cell speed dependency upon number of tracks

    Started by Jarvsiri, 7th October 2017 19:04
    •  
    •  
  12. Electromigration fail on Vdd track in standard cell

    Started by Jarvsiri, 6th October 2017 21:36
    • Replies: 3
    • Views: 433
    7th October 2017, 01:47 Go to last post
  13. Metal Spacing estimation

    Started by saha.123, 5th October 2017 06:55
    • Replies: 2
    • Views: 398
    6th October 2017, 22:00 Go to last post
  14. [SOLVED] Including a design library to Cadence

    Started by ashrafsazid, 6th October 2017 10:02
    • Replies: 1
    • Views: 232
    6th October 2017, 10:15 Go to last post
  15. Mask Verification - EB Data or Source Data

    Started by zildjiansplaash, 5th October 2017 02:18
    • Replies: 1
    • Views: 310
    5th October 2017, 12:19 Go to last post
  16. Is it good to use a Pad with only one diode as ESD

    Started by bio_man, 4th October 2017 21:22
    • Replies: 1
    • Views: 372
    4th October 2017, 23:09 Go to last post
  17. Is it good to copy and paste the Layout in Cadence?

    Started by bio_man, 2nd October 2017 14:37
    • Replies: 4
    • Views: 449
    2nd October 2017, 19:30 Go to last post
  18. SRAM Write delay and read delay in Hspice

    Started by aminfarahbakhsh, 30th September 2017 18:48
    • Replies: 0
    • Views: 430
    30th September 2017, 18:48 Go to last post
  19. HSPICE: create pulse signal with time-varying magnitude

    Started by zhanxin319, 29th September 2017 23:27
    • Replies: 1
    • Views: 446
    30th September 2017, 06:51 Go to last post
  20. Design of Single stage OTA with following specs

    Started by prateekj212, 27th September 2017 16:43
    • Replies: 6
    • Views: 658
    29th September 2017, 08:37 Go to last post
    • Replies: 8
    • Views: 744
    28th September 2017, 20:08 Go to last post
  21. transistor region in Cadence

    Started by bio_man, 27th September 2017 19:22
    • Replies: 7
    • Views: 502
    28th September 2017, 12:54 Go to last post
  22. [moved] Analog circuit Design Vs Analog layout Design

    Started by apd.Karthik, 27th September 2017 09:45
    • Replies: 2
    • Views: 415
    27th September 2017, 19:35 Go to last post
  23. Antenna violation problem in vlsi layout

    Started by Jarvsiri, 26th September 2017 20:26
    • Replies: 3
    • Views: 377
    27th September 2017, 17:29 Go to last post
  24. Fingering effect on analog layout and standard cell layout

    Started by Jarvsiri, 26th September 2017 20:16
    • Replies: 3
    • Views: 408
    27th September 2017, 14:18 Go to last post
  25. Moved: Tool to find CONTROLLABILITY & OBSERVABILITY values

    Started by reshma.k, 27th September 2017 06:08
    •  
    •  
  26. Memory layout problem in fingering and sharing

    Started by Jarvsiri, 26th September 2017 20:21
    • Replies: 1
    • Views: 333
    26th September 2017, 23:50 Go to last post