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Forum: Analog Integrated Circuit (IC) Design, Layout and Fabrication

Analog Integrated Circuit Design, Layout & Fabrication Questions. Analog ASIC Design. Semiconductor Technology Issues.

  1. Sticky Thread Sticky: Featured Reference Designs

    Started by mmatheson, 16th June 2016 22:04
    • Replies: 0
    • Views: 5,956
    16th June 2016, 22:04 Go to last post
  2. Sticky Thread Sticky: Read this before posting

    Started by klug, 3rd December 2007 18:00
    • Replies: 0
    • Views: 25,103
    3rd December 2007, 18:00 Go to last post
    • Replies: 1
    • Views: 52
    Yesterday, 17:08 Go to last post
  1. DRC errors after dummy metal fill

    Started by amitga, Yesterday 12:26
    • Replies: 0
    • Views: 46
    Yesterday, 12:26 Go to last post
  2. How to Reduce BJT Base Current Mismatch

    Started by ljp2706, 17th October 2017 18:48
    • Replies: 6
    • Views: 349
    18th October 2017, 12:36 Go to last post
    • Replies: 1
    • Views: 107
    18th October 2017, 10:14 Go to last post
    • Replies: 12
    • Views: 1,211
    18th October 2017, 07:17 Go to last post
  3. [moved] Delaying a square signal

    Started by Wheatley, 17th October 2017 11:14
    • Replies: 10
    • Views: 253
    18th October 2017, 04:38 Go to last post
  4. Question on simulating LO leakage for a transmitter

    Started by abcyin, 17th October 2017 07:54
    • Replies: 8
    • Views: 212
    18th October 2017, 04:30 Go to last post
  5. Determine Technology Current using foundry models

    Started by deveshkm, 9th August 2017 08:03
    2 Pages
    1 2
    • Replies: 34
    • Views: 2,835
    17th October 2017, 17:41 Go to last post
  6. silicon dioxide in mosfets for gate insulation

    Started by chaithanyateja9, 16th October 2017 04:28
    • Replies: 4
    • Views: 237
    17th October 2017, 02:13 Go to last post
  7. need information about MOSIS company

    Started by ultrasonic.1991, 16th October 2017 14:51
    • Replies: 1
    • Views: 171
    16th October 2017, 15:08 Go to last post
  8. Technology nodes and Circuit design variation

    Started by kaushikrvs, 14th October 2017 08:22
    • Replies: 1
    • Views: 414
    14th October 2017, 18:15 Go to last post
  9. Calibre xRC Extraction Device Overlap

    Started by ljp2706, 5th October 2017 13:26
    • Replies: 11
    • Views: 829
    13th October 2017, 13:58 Go to last post
  10. Moved: RE: differential loss cadence

    Started by kenambo, 12th October 2017 11:58
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  11. Moved: DC DC Converter parameters

    Started by gkkrish52, 12th October 2017 08:48
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  12. Moved: Is it possible to create our own IC in Pspice software?

    Started by letlive, 11th October 2017 18:01
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  13. Moved: Comparator Desing paper

    Started by Ali_sh, 9th October 2017 19:38
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  14. diode model for Cadence

    Started by bio_man, 8th October 2017 03:38
    • Replies: 13
    • Views: 777
    9th October 2017, 19:05 Go to last post
  15. Optimizer in Cadence ADE-GXL

    Started by pancho_hideboo, 9th October 2017 11:44
    • Replies: 0
    • Views: 277
    9th October 2017, 11:44 Go to last post
  16. Latchup prevention using Deep Nwell

    Started by Jarvsiri, 7th October 2017 19:07
    • Replies: 1
    • Views: 357
    8th October 2017, 17:19 Go to last post
  17. Moved: standard cell speed dependency upon number of tracks

    Started by Jarvsiri, 7th October 2017 19:04
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  18. Electromigration fail on Vdd track in standard cell

    Started by Jarvsiri, 6th October 2017 21:36
    • Replies: 3
    • Views: 499
    7th October 2017, 01:47 Go to last post
  19. Metal Spacing estimation

    Started by saha.123, 5th October 2017 06:55
    • Replies: 2
    • Views: 463
    6th October 2017, 22:00 Go to last post
  20. [SOLVED] Including a design library to Cadence

    Started by ashrafsazid, 6th October 2017 10:02
    • Replies: 1
    • Views: 292
    6th October 2017, 10:15 Go to last post
  21. Mask Verification - EB Data or Source Data

    Started by zildjiansplaash, 5th October 2017 02:18
    • Replies: 1
    • Views: 372
    5th October 2017, 12:19 Go to last post
  22. Is it good to use a Pad with only one diode as ESD

    Started by bio_man, 4th October 2017 21:22
    • Replies: 1
    • Views: 435
    4th October 2017, 23:09 Go to last post
  23. Is it good to copy and paste the Layout in Cadence?

    Started by bio_man, 2nd October 2017 14:37
    • Replies: 4
    • Views: 512
    2nd October 2017, 19:30 Go to last post
  24. SRAM Write delay and read delay in Hspice

    Started by aminfarahbakhsh, 30th September 2017 18:48
    • Replies: 0
    • Views: 492
    30th September 2017, 18:48 Go to last post
  25. HSPICE: create pulse signal with time-varying magnitude

    Started by zhanxin319, 29th September 2017 23:27
    • Replies: 1
    • Views: 501
    30th September 2017, 06:51 Go to last post
  26. Design of Single stage OTA with following specs

    Started by prateekj212, 27th September 2017 16:43
    • Replies: 6
    • Views: 720
    29th September 2017, 08:37 Go to last post
    • Replies: 8
    • Views: 812
    28th September 2017, 20:08 Go to last post