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Forum: Analog Integrated Circuit (IC) Design, Layout and Fabrication

Analog Integrated Circuit Design, Layout & Fabrication Questions. Analog ASIC Design. Semiconductor Technology Issues.

  1. Sticky Thread Sticky: [SOLVED] LIN transceivers that save board space & cost

    Started by B. David Miyares, 2nd April 2018 14:01
    • Replies: 0
    • Views: 261
    2nd April 2018, 14:01 Go to last post
  2. Sticky Thread Sticky: Read this before posting

    Started by klug, 3rd December 2007 18:00
    • Replies: 0
    • Views: 27,648
    3rd December 2007, 18:00 Go to last post
    • Replies: 1
    • Views: 2
    Today, 16:22 Go to last post
  1. Common Centroid Capacitor Layout in Cadence

    Started by Puppet123, 17th April 2018 22:22
    • Replies: 3
    • Views: 122
    Today, 15:26 Go to last post
    • Replies: 3
    • Views: 79
    Today, 15:08 Go to last post
  2. MMWave Layout Issues in CMOS

    Started by Puppet123, 19th April 2018 02:30
    • Replies: 10
    • Views: 247
    Today, 11:06 Go to last post
  3. VCO gain and tuning range

    Started by posiba, Yesterday 08:43
    • Replies: 2
    • Views: 81
    Yesterday, 13:44 Go to last post
  4. Layer definition in TSMC 65nm

    Started by AllenD, 18th April 2018 04:49
    • Replies: 2
    • Views: 124
    Yesterday, 10:35 Go to last post
  5. Mismatch simulation Schematic vs. Layout

    Started by DefconNowhere, 19th April 2018 16:23
    • Replies: 2
    • Views: 105
    Yesterday, 08:59 Go to last post
    • Replies: 3
    • Views: 100
    19th April 2018, 23:13 Go to last post
    • Replies: 8
    • Views: 1,070
    19th April 2018, 18:31 Go to last post
  6. Balanced OTA-C cascode IC design

    Started by sherif96, 23rd March 2018 15:03
    3 Pages
    1 2 3
    • Replies: 43
    • Views: 1,576
    19th April 2018, 17:11 Go to last post
  7. Abutting transistors in TSMC65nm

    Started by Puppet123, 17th April 2018 22:35
    • Replies: 2
    • Views: 140
    18th April 2018, 20:04 Go to last post
    • Replies: 2
    • Views: 168
    18th April 2018, 18:55 Go to last post
    • Replies: 8
    • Views: 387
    18th April 2018, 08:03 Go to last post
    • Replies: 3
    • Views: 224
    17th April 2018, 22:28 Go to last post
  8. Long start-up time current reference

    Started by chandlerbing65nm, 17th April 2018 09:03
    • Replies: 2
    • Views: 112
    17th April 2018, 21:06 Go to last post
  9. offset voltage of opamp

    Started by chandlerbing65nm, 17th April 2018 16:33
    • Replies: 2
    • Views: 115
    17th April 2018, 20:57 Go to last post
  10. Current Reference SS problem

    Started by chandlerbing65nm, 15th April 2018 23:57
    • Replies: 1
    • Views: 163
    16th April 2018, 19:06 Go to last post
  11. Current Mirror Inaccuracy

    Started by chandlerbing65nm, 15th April 2018 19:58
    • Replies: 2
    • Views: 179
    15th April 2018, 21:22 Go to last post
  12. Transmission Gate Impedance Problem

    Started by andreneil15, 7th April 2018 05:47
    • Replies: 8
    • Views: 398
    15th April 2018, 03:18 Go to last post
  13. Common Centroid Layout

    Started by Puppet123, 12th April 2018 20:56
    • Replies: 5
    • Views: 320
    14th April 2018, 07:07 Go to last post
  14. Cadence Layout - Interdigitization

    Started by Puppet123, 13th April 2018 23:46
    • Replies: 1
    • Views: 208
    14th April 2018, 04:28 Go to last post
  15. characterizing semiconductors

    Started by Madbunny1, 12th April 2018 19:10
    • Replies: 2
    • Views: 176
    12th April 2018, 20:41 Go to last post
  16. Current mirror transistor connection

    Started by akbarza, 26th March 2018 12:56
    • Replies: 2
    • Views: 436
    12th April 2018, 15:09 Go to last post
    • Replies: 1
    • Views: 211
    12th April 2018, 15:04 Go to last post